Systems, methods and apparatus for superconducting demultiplexer circuits

A superconducting demultiplexer comprising:

• a plurality of latching qubits that includes a lead latching qubit, a first set of latching qubits, and a second set of latching qubits, wherein each latching qubit in the plurality of latching qubits comprises a qubit loop formed by a loop of material that is superconducting below a critical temperature, and a compound Josephson junction that interrupts the qubit loop, the compound Josephson junction comprising a loop of material that is superconducting below a critical temperature that is interrupted by at least two Josephson junctions;
• a first set of clock signal lines;
• a second set of clock signal lines;
• and
• at least one control line, wherein each latching qubit in the first and the second sets of latching qubits is positioned to receive signals by inductive coupling to a control line;
• wherein the lead latching qubit is positioned to receive signals from an input signal source, a first latching qubit in the first set of latching qubits is positioned to inductively couple to the qubit loop of the lead latching qubit and a first clock signal line from the first set of clock signal lines is positioned to controllably inductively couple to the compound Josephson junction of the first latching qubit in the first set of latching qubits, a second latching qubit in the first set of latching qubits is positioned to inductively couple to the qubit loop of the lead latching qubit and a first clock signal line from the second set of clock signal lines is positioned to controllably inductively couple to the compound Josephson junction of the second latching qubit in the first set of latching qubits;
• and
• wherein the qubit loop of each latching qubit in the first set of latching qubits is respectively positioned to inductively couple to the qubit loop of three other latching qubits in the plurality of latching qubits, the compound Josephson junction of a first proportion of latching qubits from the first set of latching qubits is positioned to inductively couple to a clock signal line from the first set of clock signal lines, the compound Josephson junction of a second proportion of latching qubits from the first set of latching qubits is positioned to inductively couple to a clock signal line from the second set of clock signal lines, the qubit loop of each latching qubit in the second set of latching qubits is positioned to inductively couple to the qubit loop of a respective one of the latching qubits in the first set of latching qubits, the compound Josephson junction of a first proportion of latching qubits in the second set of latching qubits is positioned to inductively couple to a clock signal line from the first set of clock signal lines, and the compound Josephson junction of a second proportion of latching qubits in the second set of latching qubits is positioned to inductively couple to a clock signal line from the second set of clock signal lines.

A demultiplexer circuit comprising:

• a first switching cell including an input end and two output ends;
• a first set of additional switching cells, wherein each switching cell in the first set of additional switching cells includes an input end and two output ends and wherein the first set of additional switching cells includes at least one buffer cell;
• and
• an input signal source that is configured to controllably couple input signals to the first switching cell;
• wherein the first set of additional switching cells is arranged to substantially form a binary tree such that each output end of each switching cell couples to a respective input end of another switching cell and wherein each input end of each switching cell receives at least one input from at least one output of at least one other switching cell, and wherein the input end of the at least one buffer cell receives one respective output end from each of at least two respective switching cells and the two output ends of the at least one buffer cell each couple to the input end of a respective switching cell.