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US 8,576,613 B2Granted
SRAM devices and methods of manufacturing the same
AssigneeSamsung Electronics Co., Ltd.
InventorYongshik Kim
Life of this patent
Estimating the term…
Abstract
Example embodiments relate to an SRAM device and a method of manufacturing the same. The SRAM device may include first transistors operating in a horizontal direction and second transistors that are disposed on the first transistors to operate in a vertical direction. In example embodiments, the second transistors may be vertically connected to the first transistors. In example embodiments, the second transistors may be vertical transistors that include vertical gates surrounding vertical channels.
Claims13
An SRAM device, comprising:
- first transistors configured to operate in a horizontal direction, the first transistors include first and second access transistors and first and second driver transistors electrically connected to the first and second access transistors;
- and
- second transistors on the first transistors, the second transistors configured to operate in a vertical direction, the second transistors being vertically connected to the first transistors,
- wherein the second transistors are vertical transistors including vertical gates and vertical channels surrounded by the vertical gates.
1 more element
An SRAM device, comprising:
- first transistors configured to operate in a horizontal direction, the first transistors include first and second access transistors and first and second driver transistors electrically connected to the first and second access transistors;
- and
- second transistors on the first transistors, the second transistors configured to operate in a vertical direction, the second transistors being vertically connected to the first transistors, the second transistors include first and second load transistors vertically connected to the first and second driver transistors,
- wherein the second transistors are vertical transistors including vertical gates and vertical channels surrounded by the vertical gates;
- a first serial via serially connecting the first load transistor to the first driver transistor, the first serial via comprising a first via connected to a vertical gate of the first load transistor and a first shared contact commonly connected to a horizontal gate of the first driver transistor and the first via;
- and
- a second serial via serially connecting the second load transistor to the second driver transistor, the second serial via comprising a second via connected to a vertical gate of the second load transistor and a second shared contact commonly connected to a horizontal gate of the second driver transistor and the second via.
4 more elements
An SRAM device, comprising:
- first transistors configured to operate in a horizontal direction, the first transistors include first and second access transistors and first and second driver transistors electrically connected to the first and second access transistors;
- and
- second transistors on the first transistors, the second transistors configured to operate in a vertical direction, the second transistors being vertically connected to the first transistors, the second transistors include first and second load transistors vertically connected to the first and second driver transistors,
- wherein the second transistors are vertical transistors including vertical gates and vertical channels surrounded by the vertical gates;
- a first contact connecting a vertical drain of the second load transistor to a horizontal gate of the first driver transistor;
- and
- a second contact connecting a vertical drain of the first load transistor to a horizontal gate of the second driver transistor.
4 more elements
An SRAM device, comprising:
- first transistors configured to operate in a horizontal direction, the first transistors include a first access transistor, a second access transistor, a first driver transistor, and a second driver transistor;
- and
- second transistors on the first transistors, the second transistors configured to operate in a vertical direction, the second transistors being vertically connected to the first transistors, the second transistors include a first load transistor and a second load transistor,
- the second transistors are vertical transistors including vertical gates and vertical channels surrounded by the vertical gates;
- and
- the first driver transistor and the first load transistor being serially connected to form a first inverter between the first and second access transistors, the second driver transistor and the second load transistor being serially connected to form a second inverter between the first and second access transistors, and the first and second load transistors are on the second and first driver transistors and are vertically connected to the second and first driver transistors, respectively;
- the first load transistor comprises a first vertical channel connected to a gate of the second driver transistor and a first vertical gate serially connected to a gate of the first driver transistor while surrounding the first vertical channel, and
- the second load transistor comprises a second vertical channel connected to the gate of the first driver transistor and a second vertical gate serially connected to the gate of the second driver transistor while surrounding the second vertical channel;
- a first contact connecting the second vertical channel of the second load transistor to the gate of the first driver transistor;
- and
- a second contact connecting the first vertical channel of the first load transistor to the gate of the second driver transistor.
8 more elements
An SRAM device, comprising:
- first transistors configured to operate in a horizontal direction, the first transistors include a first access transistor, a second access transistor, a first driver transistor, and a second driver transistor;
- and
- second transistors on the first transistors, the second transistors configured to operate in a vertical direction, the second transistors being vertically connected to the first transistors, the second transistors include a first load transistor and a second load transistor,
- the second transistors are vertical transistors including vertical gates and vertical channels surrounded by the vertical gates;
- and
- the first driver transistor and the first load transistor being serially connected to form a first inverter between the first and second access transistors, the second driver transistor and the second load transistor being serially connected to form a second inverter between the first and second access transistors, and the first and second load transistors are on the second and first driver transistors and are vertically connected to the second and first driver transistors, respectively;
- the first load transistor comprises a first vertical channel connected to a gate of the second driver transistor and a first vertical gate serially connected to a gate of the first driver transistor while surrounding the first vertical channel, and
- the second load transistor comprises a second vertical channel connected to the gate of the first driver transistor and a second vertical gate serially connected to the gate of the second driver transistor while surrounding the second vertical channel;
- a first serial via connecting the first vertical gate of the first load transistor to the gate of the first driver transistor;
- and
- a second serial via connecting the second vertical gate of the second load transistor to the gate of the second driver transistor.
8 more elements
Dependencies are inferred from the claim text.