Semiconductor device where logic region and DRAM are formed on same substrate

A semiconductor device having a DRAM region and a logic region embedded therein, comprising:

• a substrate having said DRAM region and said logic region respectively formed thereon;
• a first transistor formed in said DRAM region, and having a first gate insulating film;
• and
• a second transistor formed in said logic region, and having a second gate insulating film,
• wherein equivalent oxide thickness T1 of said first gate insulating film of said first transistor is smaller than 2.2 nm,
• said second transistor formed in said logic region has, at each end of the source/drain regions thereof, a pocket region which contains an impurity ion having a conductivity type different from a conductivity type of an impurity ion composing said source/drain regions,
• said first transistor formed in said DRAM region has no pocket region formed at each end of the source/drain regions thereof, and
• at least a part of said pocket region is located in surficial portions of said substrate between the source/drain regions.

A semiconductor device having a DRAM region and a logic region embedded therein, comprising:

• a substrate having said DRAM region and said logic region respectively formed thereon;
• a first transistor formed in said DRAM region, and having a first gate insulating film and a first gate electrode;
• a second transistor formed in said logic region, and having a second gate insulating film and a second gate electrode;
• and
• a negative bias generating circuit applying a negative bias voltage to said first gate electrode,
• wherein equivalent oxide thickness T1 of said first gate insulating film of said first transistor is thinner than equivalent oxide thickness T2 of said second gate insulating film of said second transistor,
• said negative bias generating circuit applies a negative bias voltage to said first gate electrode in the standby period, and
• a dose of impurity ion implanted into a channel region in said DRAM region is lower than a dose of impurity ion implanted into a channel region in said logic region.

A semiconductor device having a DRAM region and a logic region embedded therein, comprising:

• a substrate having said DRAM region and said logic region respectively formed thereon;
• a first transistor formed in said DRAM region, and having a first gate insulating film and a first gate electrode;
• a second transistor formed in said logic region, and having a second gate insulating film and a second gate electrode;
• and
• a negative bias generating circuit applying a negative bias voltage to said first gate electrode,
• wherein equivalent oxide thickness T1 of said first gate insulating film of said first transistor is smaller than 2.2 nm,
• said negative bias generating circuit applies a negative bias voltage to said first gate electrode in the standby period,
• the equivalent oxide thickness T1 of said first gate insulating film of said first transistor is thinner than the equivalent oxide thickness T2 of said second gate insulating film of said second transistor, and
• a dose of impurity ion implanted into a channel region in said DRAM region is lower than a dose of impurity ion implanted into a channel region in said logic region.