MOSFET with thin semiconductor channel and embedded stressor with enhanced junction isolation
AssigneeInternational Business Machines Corporation
InventorsKangguo Cheng, Bruce Doris, Ali Khakifirooz, Pranita Kulkarni
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Abstract
A field effect transistor structure that uses thin semiconductor on insulator channel to control the electrostatic integrity of the device. Embedded stressors are epitaxially grown in the source/drain area from a template in the silicon substrate through an opening made in the buried oxide in the source/drain region. In addition, a dielectric layer is formed between the embedded stressor and the semiconductor region under the buried oxide layer, which is located directly beneath the channel to suppress junction capacitance and leakage.
Claims15
A semiconductor structure comprising:
- a semiconductor substrate;
- a buried oxide layer having a thickness of from 10 to 50 nm within the semiconductor substrate;
- a gate stack on the semiconductor substrate, wherein a channel region having a thickness of from 5 to 10 nm is provided between the gate stack and the buried oxide layer;
- a dielectric layer adjacent to the buried oxide layer;
- a first epitaxially-grown region adjacent to the dielectric layer;
- wherein the first epitaxially-grown region has a lattice constant different from the lattice constant of the semiconductor substrate;
- and a second epitaxially-grown region adjacent to the channel region and adjacent to the first epitaxially-grown region;
- wherein the first epitaxially-grown region is undoped or has a dopant concentration of less than 1·1018 atoms/cm3 and the second epitaxially-grown region has a dopant concentration of more than 1·1019 atoms/cm3.
Dependencies are inferred from the claim text.