Implementing vertical signal repeater transistors utilizing wire vias as gate nodes
AssigneeInternational Business Machines Corporation
InventorsKarl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams
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Abstract
A method and structures are provided for implementing vertical transistors utilizing wire vias as gate nodes. The vertical transistors are high performance transistors fabricated up in the stack between the planes of the global signal routing wire, for example, used as vertical signal repeater transistors. An existing via or a supplemental vertical via between wire planes provides both an electrical connection and the gate node of the novel vertical transistor.
Claims14
A back-end-of-line (BEOL) structure for implementing vertical transistors comprising:
- a vertical field effect transistor (FET) being formed by polycrystalline depositions in a stack between planes of a respective global signal routing wire;
- a channel length being delineated by said polycrystalline depositions with sequential source deposition, channel deposition and drain deposition;
- and
- a wire via being formed defining a gate node includes forming an etched hole through said source deposition, channel deposition and drain deposition, and a dielectric layer to a signal wire in the BEOL stack;
- a thin dielectric deposited in said etched opening, and said thin dielectric removed from a bottom of said etched opening, and a metal deposited in said etched opening.
A vertical transistor fabricated in a back-end-of-line (BEOL) structure comprising:
- a plurality of polycrystalline depositions in a stack between planes of a respective global signal routing wire forming the vertical transistor;
- said plurality of polycrystalline depositions in said stack being deposited in an etched opening in a dielectric layer in the BEOL stack;
- a channel length of the vertical transistor being delineated by said polycrystalline depositions with sequential source deposition, channel deposition and drain deposition;
- and
- a wire via being formed through said polycrystalline depositions defining a gate node.
Dependencies are inferred from the claim text.