Blocking layers for leakage current reduction in DRAM devices
AssigneesIntermolecular, Inc., Elpida Memory, Inc.
InventorsSandra G. Malhotra, Hanhong Chen, Wim Y. Deweerd, Hiroyuki Ode
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Abstract
A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.
Claims20
A method for forming a capacitor stack, the method comprising:
- forming a MoO2 first electrode layer on a substrate;
- forming a TiO2 dielectric layer on the MoO2first electrode layer,
- wherein the MoO2 first electrode operates as a template promoting formation of a rutile phase of the TiO2 dielectric layer,
- wherein the TiO2 dielectric layer comprises a first dopant, and
- wherein the TiO2 dielectric layer is more than about 30% crystalline after a subsequent annealing treatment;
- forming a La2O3 blocking layer on the TiO2 dielectric layer,
- wherein the La2O3 blocking layer comprises a second dopant, and wherein the La2O3 blocking layer is amorphous after the subsequent annealing treatment;
- and
- forming a second electrode layer on the La2O3 blocking layer.
Dependencies are inferred from the claim text.