Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage
AssigneeLSI Corporation
InventorsJuergen Dirks, Matthias Dinter, Ralf Leuchter
Life of this patent
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Abstract
A method for designing an integrated circuit is disclosed. The method generally comprises the steps of (A) splitting a design layout of the integrated circuit into a plurality of tiles, (B) adding a plurality of tie-to cells to the design layout, wherein at least one of the tie-to cells generating a tie-to signal at a particular logical level is added into each of the tiles having at least one gate with an input fixed to the particular logical level and (C) routing the tie-to signal to each of the inputs within each of the tiles.
Claims19
A method of designing an integrated circuit, comprising the steps of:
- (A) generating a design layout of said integrated circuit in a computer, said design layout comprising (i) a plurality of common cells each configured to perform a logical operation and (ii) a logic gate having a logic input fixed to a logic level;
- (B) replacing at least one of said common cells proximate said logic gate with a special cell configured to (i) perform said logical operation and (ii) generate a signal at said logic level;
- (C) removing a connection that fixes said logic input of said logic gate to said logic level;
- (D) routing said signal from said special cell to said logic input of said logic gate, wherein (i) said logic gate resides inside a first of a plurality of boundaries in said design layout, (ii) said design layout further comprises a scan chain having a scan cell within said first boundary, (iii) an additional logic gate resides in a second of said boundaries and (iv) said second boundary adjoins said first boundary;
- and
- (E) marking said second boundary as full in response to said second boundary lacking available space to place another scan cell.
A method of designing an integrated circuit, comprising the steps of:
- (A) generating a design layout of said integrated circuit in a computer, said design layout comprising (i) a scan chain and (ii) a plurality of logic gates, at least one of said logic gates having a logic input fixed to a logic level and residing inside a first of a plurality of boundaries in said design layout;
- (B) adding a scan cell within said first boundary;
- (C) rerouting said logic input of said at least one logic gate to a data output of said scan cell;
- and
- (D) rerouting said scan chain to include said scan cell.
Dependencies are inferred from the claim text.