Reconfigurable logic block

A device comprising:

• a logic block, wherein the logic block includes a plurality of logic elements;
• configuration logic associated with the logic block, wherein the configuration logic is operable to identify values stored in the plurality of logic elements;
• and
• a first memory cell and a second memory cell encoded according to an encoding scheme, wherein the encoding scheme identifies a mode flag value and an enable read flag value,
• wherein the mode flag value is operable to identify whether the configuration logic stores a user defined state or a design state, wherein the configuration logic is excluded from a data verification and correction process in response to the configuration logic storing a user defined state, and wherein the configuration logic is included in the data verification and correction process in response to the configuration logic storing a design state,
• wherein the enable read flag value is operable to identify whether values stored in the configuration logic are to be read out or whether a known state is to be read out during the data verification and correction process, and
• wherein the mode flag value or enable read flag value is implemented using at least one of triple modular redundancy, larger gate area, protective capacitors, or the use of increased voltage.

A method comprising:

• determining, by a controller, whether a logic block is to be configured to store a user defined state or a design state;
• in response to determining that the logic block is to be configured to store a user defined state:
• setting, by the controller, an enable read flag value to indicate that a known state should be read out during a data verification and correction process;
• and
• setting, by the controller, a mode flag value to indicate that configuration logic should be excluded from the data verification and correction process, wherein the configuration logic is operable to identify values stored in a plurality of logic elements associated with the logic block;
• and
• in response to determining that the logic block is to be configured to store a design state:
• setting, by the controller, the mode flag value to indicate that the configuration logic should be included in the data verification and correction process;
• and
• setting, by the controller, the enable read flag value to indicate that the values stored in the configuration logic should be read out during the data verification and correction process, wherein the mode flag value or enable read flag value is implemented using at least one of triple modular redundancy, larger gate area, protective capacitors, or the use of increased voltage.