Common path pessimism removal for hierarchical timing analysis

A system for designing an integrated circuit, the system comprising:

• a processor to execute instructions;
• and
• a storage device coupled to the processor, the storage device to store instructions that when executed cause the processor to perform the operations of
• providing a hierarchical common path pessimism removal (CPPR) data base including CPPR adjustment information associated with a source latency of a capture clock of a clock port so that timing can be adjusted for common path pessimism at an end point of an internal data path of one or more partition blocks;
• querying the hierarchical CPPR data base for CPPR adjustment information associated with a clock port of a respective block of the one or more partition blocks;
• and
• adjusting timing of an internal data path ending at an end point of the respective block in response to the CPPR adjustment information to analyze timing of the respective block.

A machine readable product comprising a non-transitory machine readable storage device having machine readable instructions stored therein that when executed by a machine causes the machine to perform operations including:

• receiving a first netlist of a first partition block for a top level of a hierarchical design of an integrated circuit, the first partition block including at least one original clock signal with a pair of clock paths having an external common point outside a boundary of the first partition block;
• analyzing the pair of clock paths having the external common point to determine a first clock port and a second clock port associated with a first original clock signal at the boundary of the first partition block;
• for each of the first clock port and the second clock port,
• creating a launch clock and a capture clock,
• making exclusive clock groups for each of the launch clock for one clock port and the capture clock for the other clock port to avoid the launch clock and the capture clock for each port affecting any other internal data path within the first partition block, and
• associating common path pessimism removal (CPPR) information for the first partition block with a source latency of the launch clock so that timing is adjusted for common path pessimism at an end point of an internal data path.