Method and apparatus for performing path-level skew optimization and analysis for a logic design

A non-transitory computer readable medium including a sequence of instructions stored thereon for causing a computer to execute a method comprising:

• computing a path-level deviation from a skew schedule in the system by determining a maximum path delay and a minimum path delay for a skew domain with a timing graph modified in response to a skew schedule, and computing a difference between the maximum path delay and the minimum path delay for the skew domain;
• and
• analyzing the path-level deviation from the skew schedule in a system by determining whether the path-level deviation from the skew schedule satisfies a skew constraint.

A system designer, comprising:

• a path-level skew optimization unit that includes a delay estimation unit operable to determine a maximum path delay and minimum path delay for a skew domain in a system with a timing graph modified in response to a skew schedule, and a timing analysis unit operable to compute a difference between the maximum path delay and minimum path delay for the skew domain to determine a path-level deviation from the skew schedule in the system, and operable to analyze the path-level deviation from the skew schedule in the system by determining whether the path-level deviation from the skew schedule satisfies a skew constraint, wherein the path-level skew optimization unit is implemented in hardware.