Method and apparatus for analyzing a design of an integrated circuit using fault costs
AssigneeXilinx, Inc.
InventorsWilliam E. Leigh, Kenneth R. Weidele
Life of this patent
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Abstract
In one embodiment, a method and apparatus for analyzing a design of an integrated circuit (IC) are disclosed. For example, the method parses a netlist file of the IC where a module of the IC is parsed into a plurality of sub-modules in accordance with a hierarchical structure. The method traces through a connectivity of the plurality of sub-modules, and tabulates data associated with the connectivity with a fault cost associated with a structure of the IC.
Claims20
A method for analyzing a design of an integrated circuit (IC), comprising:
- assigning a fault cost to a plurality of endpoint structures of the IC;
- parsing a netlist file of said IC where a module of said IC is parsed into a plurality of sub-modules in accordance with a hierarchical structure until the plurality of endpoint structures of the IC is reached;
- tracing through an end-to-end connectivity of said plurality of sub-modules to produce an overall connectivity map for the IC, wherein said tracing comprises mapping each input signal and output signal of the module through the plurality of sub-modules to the plurality of endpoint structures;
- and
- tabulating data associated with the end-to-end connectivity with the fault cost assigned to at least one of the plurality of endpoint structures of the IC.
A computer-readable storage medium having stored thereon a plurality of instructions, the plurality of instructions including instructions which, when executed by a processor, cause the processor to perform steps of a method for analyzing a design of an integrated circuit (IC), comprising:
- assigning a fault cost to a plurality of endpoint structures of the IC;
- parsing a netlist file of said IC where a module of said IC is parsed into a plurality of sub-modules in accordance with a hierarchical structure until the plurality of endpoint structures of the IC is reached;
- tracing through an end-to-end connectivity of said plurality of sub-modules to produce an overall connectivity map for the IC, wherein said tracing comprises mapping each input signal and output signal of the module through the plurality of sub-modules to the plurality of endpoint structures;
- and
- tabulating data associated with the end-to-end connectivity with the fault cost assigned to at least one of the plurality of endpoint structures of the IC.
An apparatus for analyzing a design of an integrated circuit (IC), comprising:
- a processor executing a process that performs:
- assigning a fault cost to a plurality of endpoint structures of the IC;
- parsing a netlist file of said IC where a module of said IC is parsed into a plurality of sub-modules in accordance with a hierarchical structure until the plurality of endpoint structures of the IC is reached;
- tracing through an end-to-end connectivity of said plurality of sub-modules to produce an overall connectivity map for the IC that maps each input signal and output signal of the module through the plurality of sub-modules to the plurality of endpoint structures;
- and
- tabulating data associated with the end-to-end connectivity with the fault cost assigned to at least one of the plurality of endpoint structures of the IC.
Dependencies are inferred from the claim text.