Communication device employing binary product coding with selective additional cyclic redundancy check (CRC) therein

An apparatus, comprising:

• an input to receive a signal from a communication channel;
• a matrix formatting module, communicatively coupled to the input, to arrange a plurality of bits corresponding to the signal into a plurality of matrix formatted bits in accordance with a predetermined pattern such that each row and each column of the plurality of matrix formatted bits includes at least one respective control bit that is a cyclic redundancy check (CRC) bit encoded therein or an extra parity bit encoded therein;
• a plurality of row decoders to decode a plurality of rows of the plurality of matrix formatted bits to generate estimates of information bits encoded within the plurality of rows, wherein the plurality of row decoders includes first control bit functionality for generating estimates of the respective control bits encoded within the plurality of rows;
• and
• a plurality of column decoders to decode a plurality of columns of the plurality of matrix formatted bits to generate estimates of information bits encoded within the plurality of columns, wherein the plurality of column decoders includes second control bit functionality for generating estimates of the respective control bits encoded within the plurality of columns;
• and wherein:
• when a row of the plurality of rows being deemed un-decodable in a current decoding iteration:
• at least one estimate of information bits encoded within the row from at least one prior decoding iteration being selectively recovered for use in subsequent decoding performed by the plurality of column decoders;
• and
• the plurality of row decoders ignoring bits within the row affected by the plurality of column decoders from at least one prior decoding iteration.

A method, comprising:

• receiving a signal from a communication channel;
• arranging a plurality of bits corresponding to the signal into a plurality of matrix formatted bits in accordance with a predetermined pattern;
• operating a plurality of row decoders for decoding a plurality of rows of the plurality of matrix formatted bits thereby generating estimates of information bits encoded within the plurality of rows;
• operating a plurality of column decoders for decoding a plurality of columns of the plurality of matrix formatted bits thereby generating estimates of information bits encoded within the plurality of columns;
• and
• when a row of the plurality of rows being deemed un-decodable in a current decoding iteration, selectively recovering at least one estimate of information bits encoded within the row from at least one prior decoding iteration for use in subsequent decoding performed by the plurality of column decoders.