Data processing device and mobile device

A data processing device formed as a semiconductor integrated circuit to be coupled to an external memory device for performing data transmission and reception, said data processing device comprising:

• a central processing unit;
• a clock pulse generation circuit capable of generating a clock signal;
• and
• an interface unit for data transmission and reception to and from the external memory device,
• wherein said interface unit includes:
• a clock signal output terminal for outputting the clock signal generated by the clock pulse generation circuit;
• a variable delay circuit for generating a receiving clock signal by imparting delay to said clock signal;
• a plurality of external data input terminals for receiving data from the external memory device;
• and
• a plurality of latch circuits, comprising data input terminals and data clock terminals, for latching data received by said plurality of external data input terminals,
• wherein said data input terminals receive data from the external memory device via said plurality of external data input terminals, and said data clock terminals receive said receiving clock signal,
• wherein said latch circuits latch data based on said receiving clock signal,
• wherein said variable delay circuit includes a plurality of delay element circuits, generates a plurality of clock signals with different amounts of delay, and selects any of the plurality of clock signals for output as said receiving clock signal, and
• wherein said variable delay circuit includes a selector circuit which selects a signal passing through or not passing through any of the plurality of delay element circuits as said receiving clock signal;
• said data processing device further comprising:
• a register which stores a set value for determining a state of said selector circuit;
• and
• a decoder which generates a control signal for said selector circuit in accordance with the set value of the register.