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US 8,572,419 B1Granted
System-on-chip power reduction through dynamic clock frequency
AssigneeMarvell International Ltd.
InventorTimothy J. Donovan
Life of this patent
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Abstract
A dynamic clock frequency module includes a request evaluation module configured to generate a sum of requests to utilize a system bus from a plurality of modules. A frequency assignment module is configured to calculate a clock frequency for the system bus in response to the requests and adjust the clock frequency between at least two non-zero frequency values. A pulse stretch module is configured to increase a period of time that at least one of the requests is asserted in response to the sum.
Claims20
A system-on-chip comprising:
- a system bus;
- a plurality of devices configured to generate request signals to access the system bus;
- a plurality of pulse modules, each configured to (i) receive a respective one of the request signals, (ii) receive a summation signal, and (iii) lengthen a pulse of the respective one of the request signals based on the summation signal to generate an output signal, wherein the summation signal indicates a remaining number of requests by the plurality of devices for the system bus, wherein the pulse of the respective one of the request signals indicates a request for the system bus by one of the plurality of devices, and wherein each of the output signals has a respective one of the lengthened pulses;
- a summer configured to (i) receive the output signals from the plurality of pulse modules, and (ii) generate the summation signal based on the output signals;
- a frequency module configured to select a frequency based on the summation signal;
- and
- a clock generator configured to generate a clock signal having the frequency,
- wherein communication between the plurality of devices via the system bus is implemented based on the clock signal.
5 more elements
A system-on-chip comprising:
- a system bus;
- a plurality of devices configured to generate request signals to access the system bus;
- an edge detection module configured to (i) receive the request signals, (ii) detect when each of the request signals are received in an asserted state, and (iii) generate a first output signal indicating when each of the request signals are received in the asserted state;
- a transaction detection circuit configured to (i) detect conclusions of transactions between the plurality of devices, and (ii) generate a second output signal, wherein the transactions are performed based on the request signals;
- a register configured to (i) generate a third output signal having a count of a remaining number of incomplete transactions between the plurality of devices (ii) increment the count of the remaining number of incomplete transactions between the plurality of devices in response to the first output signal, and (ii) decrement the count of the remaining number of incomplete transactions between the plurality of devices in response to the second output signal;
- a frequency module configured to select a frequency based on the third output signal;
- and
- a clock generator configured to generate a clock signal having the frequency,
- wherein communication between the plurality of devices via the system bus is implemented based on the clock signal.
6 more elements
Dependencies are inferred from the claim text.