Configuration of a multilevel flash memory device

A memory device comprising:

• a processor;
• non-volatile circuitry to store configuration bits;
• random access memory;
• and
• read only memory storing
• a first code configured to be executed by the processor at a power-on of the memory device, wherein the first code, when executed, results in access of the configuration bits from the non-volatile circuitry, generation of operational timing data based on the configuration bits, and storage of the operational timing data in the random access memory;
• and
• a second code configured to be executed by the processor upon receipt of a memory access command, wherein the second code, when executed, results in access of the operational timing data from the random access memory, and implementation of a memory access operation based on the operational timing data.

A method of operating a memory device comprising:

• applying power to the memory device to initiate a power-up operation;
• performing, during the power-up operation, a one-time determination of configuration bits based on latch values stored in a plurality of latches of the memory device, and a one-time application of a conversion algorithm to the configuration bits to convert the configuration bits to operational timing data representing memory device access operation wait cycles;
• storing the operational timing data in a random access memory location of the memory device;
• receiving an externally provided command to execute an access operation on the memory device;
• in response to the received command, reading the operational timing data from the random access memory location;
• and
• performing the access operation on the memory device by applying the operational timing data read from the random access memory.