US 8,572,354 B2 · Programmable logic unit and method for translating and processing instructions using interpretation registers

Abstract

An architecture for microprocessors, in which instructions include a type identifier, selects one of several interpretation registers. The interpretation registers hold information for interpreting the opcode of each instruction, so that a stream of compressed instructions (with type identifiers) can be translated into a stream of expanded instructions. Preferably the type identifiers also distinguish sequencer instructions from processing-element instructions, and can even distinguish among different types of sequencer instructions (as well as among different types of processing-element instructions).

Claims20

Dependent claims

A programmable logic unit, comprising:

one or more programmable processing elements;
and
a sequencer which decodes instructions in an instruction stream using indirect reference to multiple interpretation registers, as specified by a Type Identifier (ID) value and an opcode value within said instructions, and sends commands derived from the instruction stream to said one or more processing elements;
wherein said interpretation registers include identifiers defining respective mappings of opcodes to one of a plurality of instruction groups, and said commands being at least partly determined by said mappings;
and
wherein said interpretation registers include operand control information that comprises a vector length and a stride between vector elements.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

11/536,483Filed 28 Sep 2006

Published

US 2008/0082799 A13 Apr 2008

Granted

29 Oct 2013

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 9/30145
Arrangements for executing machine instructions, e.g. instruction decode: instruction analysis, e.g. decoding, instruction word fields
G06F 9/3013
Organisation of register space, e.g. banked or distributed register file: according to data content, e.g. floating-point registers, address registers
G06F 9/30178
Runtime instruction translation, e.g. macros: of compressed or encrypted instructions
G06F 9/30185
Instruction operation extension or modification: according to one or more bits in the instruction, e.g. prefix, sub-opcode

Programmable logic unit and method for translating and processing instructions using interpretation registers

Life of this patent

Programmable logic unit and method for translating and processing instructions using interpretation registers

Life of this patent

Abstract

Claims20