Condensed router headers with low latency output port calculation

A computer program product tangibly stored on a computer-readable hardware storage device, the computer program for communicating among cores in a multi-core processor device that comprises a plurality of cores, each core comprising a processor and a switch, the computer program including instructions for causing the computing system to:

• route a packet that includes a header and payload from an origin core to a destination core over a route including multiple cores in the multi-core processor device;
• and
• at each core in the route before the destination core, route the packet to the next core in the route according to a value of a respective symbol in a sequence of multiple symbols in the header, with the respective symbol having a first symbol value indicating a single likely direction and the respective symbol having a second, different symbol value indicating routing according to at least one of multiple less likely routing directions.