Cache result register for quick cache information lookup

A computer implemented method for debugging a device using a debugger, the method comprising:

• forwarding to the device, while the device is in debug mode, a dummy transaction having a transaction address that triggers a cache access operation within each level of cache to determine whether the transaction address hits within a particular cache;
• wherein the forwarding of the dummy transaction while the device is in debug mode further triggers each cache to update a cache result register (CRR) of the particular cache with cache access information that indicates whether the transaction address hits within the particular cache, and when the transaction address hits within the particular cache, further indicates a way and an index at which the information corresponding to the transaction address is located within the particular cache;
• in response to completion of the dummy transaction within the device, triggering a debug probe coupled to the device to retrieve hit/miss information from the CRR and updating a memory window of the debugger with a copy of the data returned from the dummy transaction and hit/miss information corresponding to the dummy transaction for each cache within the memory hierarchy, wherein the debug probe of the debugger coupled to a debug interface of the device detects from each CRR of each cache whether the transaction address from the dummy transaction hit within the particular cache;
• and
• in response to the transaction address having hit within the particular cache, retrieves a way indicator value and an index value from the CRR and performs an access to a specific physical location within the cache indicated by the way indicator value and the index value at which the information is stored within the particular cache;
• wherein each CRR is accessible to the debug interface via a peripheral bus connecting the debug interface to the processor core and to each cache.

A method for enabling debugging within a device having a processor core and a memory hierarchy having one or more levels of cache, the method comprising:

• receiving at the processor core a transaction address associated with a dummy read, while the device is in a debug mode, wherein the processor core and each cache of the device are set to operate in the debug mode;
• in response to receipt of the transaction address, forwarding the transaction address to a first level cache of a memory hierarchy that includes one or more levels of cache and a memory;
• determining within each level of the one or more levels of cache whether the transaction address hits;
• and
• in response to a hit of the transaction address within a cache, updating a cache result register (CRR) of that particular cache with cache access information including a hit/miss indicator value and a way indicator value and an index value corresponding to a physical location within the particular cache at which the information associated with the transaction address is located.