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US 8,572,320 B1Granted
Memory devices and systems including cache devices for memory modules
AssigneeCypress Semiconductor Corporation
InventorDinesh Maheshwari
Life of this patent
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Abstract
A memory apparatus may include one or more cache memory integrated circuit (ICs), each of which may have compare circuitry that compares a received address with stored compare values, a cache memory that provides cached data in response to the compare circuitry, a controller interface having at least address and control signal input terminals, and a module output connection having at least address and control signal output terminals corresponding to the address and control signal input terminals.
Claims19
A memory apparatus, comprising:
- at least one cache memory integrated circuit (IC) comprising compare circuitry that compares a received address with stored compare values, the compare circuitry providing a configurable granularity in cache compare tries responsive to a configurable SET value;
- cache memory that provides cached data in response to the compare circuitry, a controller interface having at least address and control signal input terminals, and
- a module output connection having at least address and control signal output terminals corresponding to the address and control signal input terminals.
A method, comprising:
- including at least one cache memory integrated circuit (IC) between at least input connections of a memory module circuit board and memory control signal paths for a plurality of memory ICs formed on the memory module circuit board, and
- in response to a cache miss on the cache memory IC, placing non-accessed memory circuits on the cache memory IC into a low power consuming state and returning said non-accessed memory circuits to a higher power consuming state before a next command to the cache memory IC is expected, and
- in response to predetermined address values on the at least input connections, generating memory standby commands on the memory control signal paths for placing memory ICs into a lower power consuming state from a higher power consuming state.
A memory apparatus, comprising:
- at least one cache memory integrated circuit (IC) including at least one cache memory array that stores cached data, cache compare circuitry that generates a cache hit indication in response to address data received at module input connections, the cache compare circuitry comprising a configurable granularity in cache compare tries responsive to a configurable SET value;
- and
- a cache controller circuit, coupled to memory control output connections, that generates at least one memory device control signal compatible with predetermined memory ICs.
Dependencies are inferred from the claim text.