Bus traffic profiling
AssigneeMarvell International Ltd.
InventorsWenwei Cai, Zhenhua Wu
Life of this patent
Estimating the term…
Abstract
Methods and systems for analyzing bus traffic in a target device, such as a system on-a-chip (SOC) comprises capturing a processor event and generating an interrupt based on a threshold associated with the processor event. Based on at least the interrupt, a instruction pointer associated with the processor event that generated the interrupt is identified. An instruction analyzer identifies a memory address of the instruction associated with the processor event that generated the interrupt. At least the processor event and a associated instruction information are collected by a sample collector and transferred to a host for performance profiling.
Claims16
A method for generating a performance profile of traffic on a system bus of a target device, the method comprising:
- receiving a plurality of processor events and respective instruction information associated with each processor event, each respective instruction information including a data address;
- identifying a device element from a plurality of device elements for each of the plurality of processor events based on comparing the respective data addresses to a list of device addresses in a device database;
- generating a destination address data size pair associated with each device element identified;
- generating an actual performance profile of the system bus by sampling the destination address data size pairs;
- displaying the actual performance profile of the system bus;
- generating a model performance profile comprising a theoretical peak throughput of the system bus, wherein the model performance profile is based, at least in part, on a device model;
- and
- identifying potential performance bottlenecks in the system bus based, at least in part, on comparing the actual performance profile of the system bus with the model performance profile.
A system for profiling a performance of a system bus in a target device, the system comprising:
- a performance monitoring unit configured to capture a plurality of processor events, wherein the performance monitoring unit is coupled to a processor configured to execute an interrupt service routine that is configured to identify an instruction pointer associated with a processor event captured by the performance monitoring unit, wherein the performance monitoring unit generates an interrupt based at least in part on capturing a processor event of the plurality of processor events;
- an instruction analyzer coupled to the performance monitoring unit, wherein the instruction analyzer is configured to determine, based on the instruction pointer identified by the interrupt service routine, a memory address of an instruction associated with the interrupt;
- and
- a sample collector coupled to the instruction analyzer, wherein the sample collector is configured to
- transmit, from the instruction analyzer to a host, (i) the processor event that generates the interrupt and (ii) information associated with the instruction, and
- enable the host to (i) generate an actual performance profile of the system bus, (ii) compare the actual performance profile of the system bus with a model performance profile comprising a theoretical peak throughput of the system bus, and (iii) identify potential performance bottlenecks in the system bus based, at least in part, on the comparing the actual performance profile of the system bus with the model performance profile.
A method for analyzing a system bus in a system on a chip, the method comprising:
- capturing a processor event from the system bus;
- generating an interrupt for the processor event when a threshold defining a range of values associated with the processor event is satisfied;
- collecting instruction information associated with the processor event that generated the interrupt;
- and
- transferring the processor event and the instruction information to a host, to enable the host to
- generate an actual performance profile of the system bus from i) the processor event and ii) the instruction information,
- compare the actual performance profile of the system bus with a model performance profile comprising a theoretical peak throughput of the system bus, and
- identify potential performance bottlenecks in the system bus based, at least in part, on the comparing the actual performance profile of the system bus with the model performance profile.
Dependencies are inferred from the claim text.