Methods and apparatuses for cordic processing

A programmable logic array, comprising:

• a plurality of programmable logic blocks configured to be programmable for a variety of interconnections and a variety of functions;
• and
• a CORDIC engine operably coupled to at least some of the plurality of programmable logic blocks, the CORDIC engine comprising:
• an N-stage CORDIC processor configured for performing N micro-iterations and generating a 3-vector CORDIC output responsive to a 3-vector CORDIC input, the N-stage CORDIC processor comprising N CORDIC processors operably cascaded in series, each of the CORDIC processors comprising:
• a first variable shifter operably coupled to a first vector input and configured to generate a shifted first vector by an amount responsive to an iteration indicator from the counter;
• a second variable shifter operably coupled to a second vector input and configured to generate a shifted second vector by an amount responsive to the iteration indicator from the counter;
• a first adder/subtractor for arithmetically combining the first vector input and the shifted second vector to generate a first vector output;
• a second adder/subtractor for arithmetically combining the second vector input and the shifted first vector to generate a second vector output;
• and
• a third adder/subtractor for arithmetically combining a third vector input and a elementary angle input correlated to the iteration indicator to generate a third vector output;
• a counter configured for counting a number of M macro-iterations and indicating a start of the cycle iterations;
• and
• a multiplexer configured for selecting an input to the N-stage CORDIC processor as the 3-vector CORDIC input at the start of the cycle iterations or the 3-vector CORDIC output at other times;
• wherein the 3-vector CORDIC output is configured to be complete after N*M clock cycles by generating the N micro-iterations for each of the M macro-iterations.

A method, comprising:

• performing N micro-iterations of a CORDIC algorithm and generating a 3-vector CORDIC output responsive to a 3-vector CORDIC input by:
• variably shifting a first vector input to generate a shifted first vector by an amount responsive to an iteration indicator from the counting the number of M macro-iterations;
• variably shifting a second vector input to generate a shifted second vector by an amount responsive to the iteration indicator;
• adding or subtracting the first vector input and the shifted second vector to generate a first vector output;
• adding or subtracting the second vector input and the shifted first vector to generate a second vector output;
• and
• adding or subtracting a third vector input and a elementary angle input correlated to the iteration indicator to generate a third vector output;
• counting a number of M macro-iterations for the CORDIC algorithm and indicating a start of the cycle iterations;
• repeating the performing the N micro-iterations for each of the M macro-iterations;
• and
• selecting an input to the N-stage CORDIC processor as the 3-vector CORDIC input at the start of the cycle iterations or the 3-vector CORDIC output at other times.