Parameterization of a CORDIC algorithm for providing a CORDIC engine

A non-transitory machine-readable medium having stored thereon information representing instructions that, when executed by a processor, cause the processor to perform operations comprising:

• obtaining a number of fractional output bits for a user-defined numerical result format for each output variable of a plurality of output variables associated with a COordinate Rotation Digital Computer (CORDIC) algorithm, wherein the number of fractional output bits for at least two output variables of the plurality of output variable are different;
• defining a number of iterations for each output variable of the plurality of output variables as a function of the number of fractional output bits for that respective output variable, wherein the number of iterations for each output variable of the plurality of output variables is defined to be equal to a same constant plus the number of fractional output bits for that respective output variable, wherein the numbers of iterations for the at least two output variables are different;
• determining quantizations associated with each output variable of the plurality of output variables responsive at least in part to the number of fractional output bits for that respective output variable, and to the number of iterations for that respective output variable, and
• outputting the plurality of output variables based on the numbers of iterations and the quantizations.

A CORDIC conversion engine, comprising:

• an integrated circuit implementing a CORDIC parameterization converter;
• wherein the integrated circuit is configured for obtaining a number of fractional output bits for a user-defined numerical result format for each output variable of a plurality of output variables, wherein the number of fractional output bits for at least two output variables of the plurality of output variable are different;
• wherein the integrated circuit is also configured for defining a number of iterations for each output variable of the plurality of output variables as a function of the number of fractional output bits for that respective output variable, wherein the function comprises adding a same constant to the number of fractional output bits for each output variable of the plurality of output variables, wherein the numbers of iterations for the at least two output variables are different;
• wherein the integrated circuit is also configured for determining quantizations associated with each output variable of the plurality of output variables responsive at least in part to the number of fractional output bits for that respective output variable and to the number of iterations for that respective output variable, and
• outputting the plurality of output variables based on the numbers of iterations and the quantizations.