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US 8,572,148 B1Granted
Data reorganizer for fourier transformation of parallel data streams
AssigneeXilinx, Inc.
InventorsGabor Szedo, Hemang Parekh
Life of this patent
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Abstract
A data reorganizer for Fourier Transforms, both forward and inverse, of multiple parallel data streams input to an integrated circuit, and method for use thereof, are described. The data reorganizer has a k input commutator, for k a positive integer greater than zero; an address generator; memory buffers; and an output commutator.
Claims14
A data reorganizer, comprising:
- a first radix-k commutator for k a positive even integer greater than zero;
- wherein the first radix-k commutator is coupled to receive first parallel input streams to provide first parallel output streams;
- an address generator coupled to receive a clock signal and configured to generate select signals and address signals using the clock signal;
- memory buffers coupled to respectively receive the first parallel output streams from the first radix-k commutator and to respectively receive the address signals from the address generator;
- wherein the first parallel input streams have data in a first order;
- wherein the first radix-k commutator is coupled to receive a first select signal of the select signals and configured to reorder the first parallel input streams to rearrange the data via the first parallel output streams for segmented storage of the data in the memory buffers in a second order;
- and
- a second radix-k commutator coupled to receive second parallel input streams from the memory buffers to provide second parallel output streams;
- wherein the second radix-k commutator is coupled to receive a second select signal of the select signals and configured to reorder the second parallel input streams to rearrange the data via the second parallel output streams into a third order;
- and
- wherein the memory buffers form a single buffer stage between the first radix-k commutator and the second radix-k commutator.
8 more elements
A method, comprising:
- receiving first parallel input streams to a first radix-k commutator, for k a positive even integer greater than zero, for commutation to provide first parallel output streams;
- wherein the first parallel input streams have data in a first order;
- generating select signals and address signals by an address generator coupled to receive a clock signal;
- storing the first parallel output streams from the first radix-k commutator in memory buffers using the address signals from the address generator;
- receiving a first select signal of the select signals by the first radix-k commutator to reorder the data;
- reordering the first parallel input streams by the first radix-k commutator to rearrange the data into a second order for the first parallel output streams for segmented storage of the data in the memory buffers;
- receiving second parallel input streams from the memory buffers by a second radix-k commutator for commutation to provide second parallel output streams;
- wherein the memory buffers form a single buffer stage between the first radix-k commutator and the second radix-k commutator;
- receiving a second select signal of the select signals by the second radix-k commutator to reorder the data;
- and
- reordering the second parallel input streams by the second radix-k commutator to rearrange the data into a third order for the second parallel output streams.
8 more elements
Dependencies are inferred from the claim text.