Execution of fixed point instructions using a decimal floating point unit

A decimal floating point (DFP) circuit of a computer, the DFP circuit being configured to execute a fixed point instruction by a method including:

• accepting, by the DFP circuit of the computer, two operands, the two operands both comprising one of a DFP format and a packed binary coded decimal (BCD) format;
• executing the fixed point instruction by the DFP circuit based on the two operands both comprising the packed BCD format, wherein executing the fixed point instruction comprises:
• shifting each of the two operands to remove respective signs by first and second shifters of the DFP circuit;
• storing the shifted two operands in first and second operand registers of the DFP circuit;
• detecting any invalid BCD formats in the two operands in the first and second operand registers by checking the shifted two operands for any invalid BCD codes;
• performing a coefficient operation on the two operands in the operand registers to generate a result by a decimal adder of the DFP circuit, wherein the coefficient operation takes place directly on the BCD data comprising the accepted two or more operands, and the accepted two or more operands are not converted from another format by the DFP circuit before performing the coefficient operation, thus using the DFP circuit to perform a BCD operation comprising the coefficient operation;
• storing the result of the coefficient operation in a working register of the DFP circuit;
• determining that an exception flag exists based on the result in the working register and, based on the exception flag existing, outputting the exception flag;
• determining that a condition code exists based on the result in the working register and, based on the condition code existing, outputting the condition code;
• storing the result in a result register of the DFP circuit;
• appending a result sign to the result of the coefficient operation in the result register;
• and
• providing the result of the coefficient operation and the appended result sign from the result register as a result output of the DFP circuit in the packed BCD format;
• and
• based on the two operands both comprising the DFP format, executing a DFP instruction by the first and second operand registers, the decimal adder, the working register, and the result register of the DFP circuit;
• wherein executing the DFP instruction comprises:
• expanding each of the two operands by first and second densely packed decimal (DPD) to BCD expanders of the DFP circuit;
• and
• storing the expanded two operands in the first and second operand registers of the DFP circuit;
• performing, by a rotator and the decimal adder of the DFP circuit, a coefficient operation on the two operands in the operand registers to generate the result;
• rounding the result by the decimal adder;
• storing the rounded result of the coefficient operation in a working register of the DFP circuit;
• appending an exponent to the result of the coefficient operation by a BCD to DPD expander of the DFP circuit;
• storing the result and the appended exponent in the result register of the DFP circuit;
• and
• providing the result of the coefficient operation and the appended exponent as a result output of the DFP circuit in the DFP format.

A hardware product comprising a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for facilitating a method for using a decimal floating point (DFP) circuit to execute a fixed point instruction, the method including:

• accepting, by the DFP circuit of a computer, two operands, the two operands both comprising one of a DFP format and a packed binary coded decimal (BCD) format;
• executing the fixed point instruction by the DFP circuit based on the two operands both comprising the packed BCD format, wherein executing the fixed point instruction comprises:
• shifting each of the two operands to remove respective signs by first and second shifters of the DFP circuit;
• storing the shifted two operands in first and second operand registers of the DFP circuit;
• detecting any invalid BCD formats in the two operands in the first and second operand registers by checking the shifted two operands for any invalid BCD codes;
• performing a coefficient operation on the two operands in the operand registers to generate a result by a decimal adder of the DFP circuit, wherein the coefficient operation takes place directly on the BCD data comprising the accepted two or more operands, and the accepted two or more operands are not converted from another format by the DFP circuit before performing the coefficient operation, thus using the DFP circuit to perform a BCD operation comprising the coefficient operation;
• storing the result of the coefficient operation in a working register of the DFP circuit;
• determining that an exception flag exists based on the result in the working register and, based on the exception flag existing, outputting the exception flag;
• determining that a condition code exists based on the result in the working register and, based on the condition code existing, outputting the condition code;
• storing the result in a result register of the DFP circuit;
• appending a result sign to the result of the coefficient operation in the result register;
• and
• providing the result of the coefficient operation and the appended result sign from the result register as a result output of the DFP circuit in the packed BCD format;
• and
• based on the two operands both comprising the DFP format, executing a DFP instruction by the first and second operand registers, the decimal adder, the working register, and the result register of the DFP circuit;
• wherein executing the DFP instruction comprises:
• expanding each of the two operands by first and second densely packed decimal (DPD) to BCD expanders of the DFP circuit;
• and
• storing the expanded two operands in the first and second operand registers of the DFP circuit;
• performing, by a rotator and the decimal adder of the DFP circuit, a coefficient operation on the two operands in the operand registers to generate the result;
• rounding the result by the decimal adder;
• storing the rounded result of the coefficient operation in a working register of the DFP circuit;
• appending an exponent to the result of the coefficient operation by a BCD to DPD expander of the DFP circuit;
• storing the result and the appended exponent in the result register of the DFP circuit;
• and
• providing the result of the coefficient operation and the appended exponent as a result output of the DFP circuit in the DFP format.