Scanning line driving circuit

A scanning line driving circuit comprising a multi-stage shift register, wherein:

• each stage of said multi-stage shift register comprises:
• an output terminal for outputting an output signal;
• a first input terminal receiving an output signal of a preceding stage;
• a second input terminal receiving an output signal of a subsequent stage;
• a first voltage signal terminal supplied with a first voltage signal;
• a second voltage signal terminal supplied with a second voltage signal;
• a clock terminal;
• a first transistor supplying a clock signal input to said clock terminal to said output terminal;
• a second transistor discharging said output terminal;
• a third transistor connected between a first node connected with a control electrode of said first transistor and said first voltage signal terminal and including a control electrode connected to said first input terminal;
• and
• a fourth transistor connected between said first node and said second voltage signal terminal and including a control electrode connected to said second input terminal;
• each stage of said multi-stage shift register changes a scanning direction by switching levels of said first and second voltage signals;
• in a case where a control electrode of said second transistor is connected to a second node at each stage of said multi-stage shift register, the stages other than said first stage and said last stage each further comprise:
• a fifth transistor connected between said second node and said second voltage signal terminal and including a control electrode connected to said first input terminal;
• and
• a sixth transistor connected between said second node and said first voltage signal terminal and including a control electrode connected to said second input terminal;
• said first stage further comprises:
• a first control signal terminal supplied with a first control signal;
• a seventh transistor connected between said second node and said first control signal terminal and including a control electrode connected to said first input terminal;
• and
• an eighth transistor connected between said second node and said first voltage signal terminal and including a control electrode connected to said second input terminal;
• said last stage further comprises:
• a second control signal terminal supplied with a second control signal;
• a ninth transistor connected between said second node and said second voltage signal terminal and including a control electrode connected to said first input terminal;
• and
• a tenth transistor connected between said second node and said second control signal terminal and including a control electrode connected to said second input terminal.