Address multiplexing in pseudo-dual port memory
AssigneeQUALCOMM Incorporated
InventorsChang Ho Jung, Cheng Zhong
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Abstract
A pseudo-dual port memory address multiplexing system includes a control circuit operative to identify a read request and a write request to be accomplished during a single clock cycle. A self time tracking circuit monitors a read operation and generates a switching signal when the read operation is determined to be complete. A multiplexer is responsive to the switching signal for selectively providing a read address and a write address to a memory address unit at the proper time.
Claims39
A pseudo dual port memory address multiplexing system comprising:
- a read port address latch operable to hold a read address in response to an external signal;
- a write port address latch operable to hold a write address in response to the external signal;
- a control circuit that controls read/write memory access based upon monitoring of a first memory operation by sending a switch signal;
- and
- a multiplexer that switches between a held read address and a held write address in response to the switch signal from the control circuit.
A pseudo dual port memory address multiplexing method comprising:
- holding a read address in a memory in response to an external signal;
- holding a write address in response to the external signal;
- controlling read/write memory access based upon monitoring of a first memory operation by sending a switch signal;
- and
- switching between a held read address and a held write address in response to the switch signal.
A pseudo dual port memory address multiplexing method comprising the steps of:
- holding a read address in a memory in response to an external signal;
- holding a write address in response to the external signal;
- controlling read/write memory access based upon monitoring of a first memory operation by sending a switch signal;
- and
- switching between a held read address and a held write address in response to the switch signal.
A pseudo dual port memory address multiplexing apparatus comprising:
- means for holding a read address in a memory in response to an external signal;
- means for holding a write address in the memory in response to the external signal;
- means for controlling read/write memory access based upon monitoring of a first memory operation by sending a switch signal;
- and
- means for switching between a held read address and a held write address in response to the switch signal.
The apparatus according to claim. 32, further comprising means for identifying read/write, read only, and write only modes of operation.
Dependencies are inferred from the claim text.