Flash memory devices and systems
AssigneeCypress Semiconductor Corporation
InventorsRyan T. Hirose, Bogdan Georgescu, Ashish Amonkar, Sean Mulholland, Vijay Raghavan, Cristinel Zonte
Life of this patent
Estimating the term…
Loading patent…
AssigneeCypress Semiconductor Corporation
InventorsRyan T. Hirose, Bogdan Georgescu, Ashish Amonkar, Sean Mulholland, Vijay Raghavan, Cristinel Zonte
Estimating the term…
Flash memory devices and systems are provided. One flash memory device includes an n-channel metal oxide semiconductor field-effect transistor (nMOSFET), a silicon-oxide-nitride-oxide silicon (SONOS) transistor coupled to the nMOSFET, and an isolated p-well coupled to the nMOSFET and the SONOS transistor. A flash memory system includes an array of memory devices divided into a plurality of paired sectors, a global bit line (GBL) configured to provide high voltage to each respective sector during erase and program operations coupled to each of the plurality of sectors, and a plurality of sense amplifiers coupled between a respective pair of sectors. Methods for operating a flash memory are also provided. One method includes providing high voltage, via the GBL, to the paired sectors during erase and program operations and providing low voltage, via a local bit line, to each memory device during read operations.
A memory device, comprising:
A non-volatile (NV) memory, comprising:
A method for operating a flash memory system comprising an array of memory devices divided into a plurality of paired sectors, a global bit line (GBL) coupled to each of the plurality of sectors, and a local bit line (BL) coupled to each memory device, the method comprising:
Dependencies are inferred from the claim text.