NAND architecture memory with voltage sensing

A method of operating a NAND architecture non-volatile memory device, comprising:

• placing a precharge voltage on one or more first bit lines and one or more second bit lines;
• coupling the one or more first bit lines to one or more selected NAND strings, wherein one or more control gates of one or more unselected memory cells of each selected NAND string are driven by a read pass voltage, and where a control gate of a selected memory cell is driven by a read voltage;
• coupling the one or more second bit lines to one or more reference NAND strings, wherein one or more control gates of one or more unselected memory cells of each reference NAND string are driven by a read pass voltage, and where a control gate of a reference memory cell is driven by a read voltage;
• and
• sensing the difference between a voltage level of each of the one or more first bit lines and a voltage level of each of the one or more second bit lines to determine a threshold voltage level of the selected non-volatile memory cells of each selected NAND string;
• wherein the NAND architecture non-volatile memory device is a multi-level cell (MLC) memory device and where the one or more unselected memory cells of each of the one or more reference NAND strings are programmed, one or more reference memory cells of each of the one or more reference NAND strings are partially programmed, and a reference memory cell of each of the one or more reference NAND strings is erased.

A method of sensing a data value in a memory cell of a non-volatile NAND architecture memory string, comprising:

• applying a precharge voltage to a selected bit line and a reference bit line;
• applying a read voltage to a selected word line coupled to a selected non-volatile memory cell of the NAND architecture memory string that is selected for reading;
• applying a pass voltage to one or more unselected word lines and coupled non-volatile memory cells of the non-volatile NAND architecture memory string;
• coupling the non-volatile NAND architecture memory string to a source line and the bit line;
• applying a read voltage to a selected word line coupled to a selected reference memory cell of a reference non-volatile NAND architecture memory string;
• applying a pass voltage to one or more unselected word lines and coupled non-volatile memory cells of the reference non-volatile NAND architecture memory string;
• coupling the reference non-volatile NAND architecture memory string to a source line and the reference bit line;
• and
• sensing a voltage difference between the bit line and the reference bit line to determine a data value stored in the selected non-volatile memory cell of the non-volatile NAND architecture memory string;
• wherein the non-volatile NAND architecture memory string is a single level cell (SLC) memory string and where the one or more unselected memory cells of the reference NAND string are programmed and the reference memory cell is erased.

A method of sensing a data value in a memory cell of a non-volatile NAND architecture memory string, comprising:

• applying a precharge voltage to a selected bit line and a reference bit line;
• applying a read voltage to a selected word line coupled to a selected non-volatile memory cell of the NAND architecture memory string that is selected for reading;
• applying a pass voltage to one or more unselected word lines and coupled non-volatile memory cells of the non-volatile NAND architecture memory string;
• coupling the non-volatile NAND architecture memory string to a source line and the bit line;
• applying a read voltage to a selected word line coupled to a selected reference memory cell of a reference non-volatile NAND architecture memory string;
• applying a pass voltage to one or more unselected word lines and coupled non-volatile memory cells of the reference non-volatile NAND architecture memory string;
• coupling the reference non-volatile NAND architecture memory string to a source line and the reference bit line;
• and
• sensing a voltage difference between the bit line and the reference bit line to determine a data value stored in the selected non-volatile memory cell of the non-volatile NAND architecture memory string;
• wherein the non-volatile NAND architecture memory string is a multi-level cell (MLC) memory string and where the one or more unselected memory cells of the reference NAND string are programmed, one or more reference memory cells of the reference NAND string are partially programmed, and a reference memory cell of the reference NAND string is erased.

A non-volatile NAND architecture memory device, comprising:

• a NAND architecture non-volatile memory array having a plurality of memory blocks;
• a differential voltage sense amplifier circuit coupled to the array;
• and
• a control circuit, wherein the control circuit and differential voltage sense amplifier circuit are adapted to read memory cells in a selected memory block of the non-volatile memory array by,
• placing a precharge voltage on one or more first bit lines and one or more second bit lines,
• coupling the one or more first bit lines to one or more selected NAND strings, wherein one or more control gates of one or more unselected memory cells of each selected NAND string are driven by a read pass voltage, and where a control gate of a selected memory cell is driven by a read voltage,
• coupling the one or more second bit lines to one or more reference NAND strings, wherein one or more control gates of one or more unselected memory cells of each reference NAND string are driven by a read pass voltage, and where a control gate of a reference memory cell is driven by a read voltage, and
• sensing the difference between a voltage level of each of the one or more first bit lines and a voltage level of each of the one or more second bit lines to determine a threshold voltage level of the selected non-volatile memory cells of each selected NAND string;
• wherein the non-volatile NAND architecture memory device is a single level cell (SLC) memory device and where the one or more unselected memory cells of each reference NAND string are programmed and the reference memory cell is erased.

A non-volatile NAND architecture memory device, comprising:

• a NAND architecture non-volatile memory array having a plurality of memory blocks;
• a differential voltage sense amplifier circuit coupled to the array;
• and
• a control circuit, wherein the control circuit and differential voltage sense amplifier circuit are adapted to read memory cells in a selected memory block of the non-volatile memory array by,
• placing a precharge voltage on one or more first bit lines and one or more second bit lines,
• coupling the one or more first bit lines to one or more selected NAND strings, wherein one or more control gates of one or more unselected memory cells of each selected NAND string are driven by a read pass voltage, and where a control gate of a selected memory cell is driven by a read voltage,
• coupling the one or more second bit lines to one or more reference NAND strings, wherein one or more control gates of one or more unselected memory cells of each reference NAND string are driven by a read pass voltage, and where a control gate of a reference memory cell is driven by a read voltage, and
• sensing the difference between a voltage level of each of the one or more first bit lines and a voltage level of each of the one or more second bit lines to determine a threshold voltage level of the selected non-volatile memory cells of each selected NAND string;
• wherein the non-volatile NAND architecture memory device is a multi-level cell (MLC) memory device and where the one or more unselected memory cells of each reference NAND string are programmed, one or more reference memory cells of each reference NAND string are partially programmed, and a reference memory cell of each reference NAND string is erased.