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US 8,570,806 B2Granted
Z-direction decoding for three dimensional memory array
AssigneeMacronix International Co., Ltd.
InventorGuanru Lee
Life of this patent
Estimating the term…
Abstract
The switch transistors in the NAND strings have combinations of threshold voltage levels that vary across the levels of a three dimensional memory array. A bias arrangement is applied to the select lines electrically coupled to the switch transistors. The NAND strings on a particular level of a three dimensional memory array are selected. The NAND strings on other levels are deselected.
Claims20
An integrated circuit comprising:
- a three dimensional memory array including a plurality of levels, levels in the plurality of levels including respective two dimensional arrays of NAND strings, the NAND strings including memory cells and switch transistors, the switch transistors having combinations of threshold voltage levels that vary across the plurality of levels;
- a plurality of select lines electrically coupled to the switch transistors;
- and
- control circuitry applying a bias arrangement to the plurality of select lines such that the NAND strings on a particular level of the plurality of levels are selected by the switch transistors, and the NAND strings on other levels of the plurality of levels are deselected by the switch transistors.
1 more element
A method comprising:
- selecting NAND strings including memory cells and switch transistors on a particular level of a plurality of levels of a three dimensional memory array, and deselecting NAND strings on other levels of the plurality of levels, by applying a bias arrangement to a plurality of select lines electrically coupled to the switch transistors having combinations of threshold voltage levels that vary across the plurality of levels.
Dependencies are inferred from the claim text.