Nonvolatile semiconductor memory device capable of speeding up write operation

A nonvolatile semiconductor memory device comprising:

• a memory cell array including a plurality of blocks, each block including a plurality of strings, the plurality of strings including a first string and a second string, the first string including a plurality of first memory cells, the second string including a plurality of second memory cells, the plurality of first memory cells being connected to first word lines respectively, the plurality of second memory cells being connected to second word lines respectively, the plurality of first memory cells and the plurality of second memory cells being stacked above a semiconductor substrate;
• and
• a controller configured to control a first program operation and a second program operation, the controller configured to supply a first voltage to a selected first word line at a beginning of the first program operation,
• the controller configured to supply a second voltage to the selected first word line after supplying the first voltage, the second voltage being generated by adding a step-up voltage to the first voltage in the first program operation,
• the controller configured to supply a third voltage to a selected second word line at the beginning of the second program operation after the first program operation, a difference between the first voltage and the third voltage being substantially k (k is a natural number) times width of the step-up voltage.

A method of controlling a nonvolatile semiconductor memory system, the nonvolatile semiconductor memory system including a memory cell array, the memory cell array including a first string and a second string, the first string including a plurality of first memory cells, the second string including a plurality of second memory cells, the plurality of first memory cells being connected to first word lines respectively, the plurality of second memory cells being connected to second word lines respectively, the plurality of first memory cells and the plurality of second memory cells being stacked above a semiconductor substrate, the method comprising:

• executing a first program operation;
• and
• executing a second program operation;
• applying a first voltage to a selected first word line at the beginning of the first program operation, and applying a second voltage to the selected first word line after applying the first voltage in the first program operation, the second voltage being generated by adding a step-up voltage to the first voltage, and
• applying a third voltage to a selected second word line at the beginning of the second program operation after the first program operation, a difference between the first voltage and the third voltage being substantially k (k is natural number) times width of the step-up voltage.