Circuit and method of word line suppression

A method of generating a suppressed word line voltage comprising the steps of:

• coupling a word line to a suppressed word line voltage node;
• charging the suppressed word line voltage node to a suppressed word line voltage with a first transistor device;
• after the word line voltage node reaches the suppressed word line voltage, turning the first transistor device off;
• and
• after turning the first transistor device off, maintaining the suppressed word line voltage node at the suppressed word line voltage, using a second transistor device.

A static random access memory (SRAM) comprising:

• a first bit cell of a static random access memory (SRAM) including cross coupled inverters configured for storing and retrieving a logic state;
• a word line coupled to the first bit cell wherein the first bit cell is accessible via bit line connections through a passing gate transistor of the first bit cell controlled by the word line;
• a word line driver circuit configured to provide a word line signal at the word line to drive the first bit cell during a memory access cycle, the word line driver circuit comprising:
• a switch configured to selectively couple the word line to a suppressed word line voltage node;
• and
• a word line charging circuit coupled between a high power supply node and the suppressed word line voltage node, the word line charging circuit comprising a first transistor device responsive to a control, pulse for charging the suppressed word line voltage node to a suppressed word line voltage and a second transistor device for maintaining the suppressed word line voltage.