Memory devices and methods for high random transaction rate
AssigneeCypress Semiconductor Corporation
InventorsDinesh Maheshwari, Bruce Jeffrey Barbara, John Marino
Life of this patent
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Abstract
A memory device can include a plurality of double data rate data (DDR) ports, each configured to receive write data and output read data on a same set of data lines independently and concurrently in synchronism with at least a first clock signal; an address port configured to receive address values on consecutive, different transitions of a second clock, each address value corresponding to an access on a different one of the data ports; and a memory array section comprising a plurality of banks, each bank providing pipelined access to storage locations therein.
Claims20
A memory device, comprising:
- a plurality of double data rate data (DDR) ports, each configured to receive write data and output read data on a same set of data lines, independently and concurrently, in synchronism with at least a first clock signal;
- an address port configured to receive address values on consecutive, different transitions of a second clock, each address value corresponding to an access on a different one of the data ports;
- and
- a memory array section comprising a plurality of banks, each bank providing pipelined access to storage locations therein.
A memory device, comprising:
- a plurality of double data rate data (DDR) ports, each configured to receive write data and output read data on a same set of data lines, independently and concurrently;
- an address decoder
- configured to enable a read or write access to a selected bank from a plurality of banks via one of a plurality of data input/output (I/O) ports in response to an address value latched on a first type transition of the first clock, and
- configured to enable a read or write access to any bank but the selected bank via another one of the data I/O ports in response to an address value latched on a second type transition that immediately follows the first type transition;
- and
- a memory array section comprising a plurality of banks, each bank providing pipelined access to storage locations therein.
A method, comprising:
- latching multiple address values within one cycle of a first clock, each address value corresponding to a different transaction of a memory device;
- and
- providing double data rate accesses via different data input/output (I/O) ports for each transaction;
- wherein
- each of the different transactions can include any of:
- a read transaction or a write transaction.
Dependencies are inferred from the claim text.