US 8,570,789 B2 · SRAM timing tracking circuit

Abstract

A static random access memory (SRAM) test apparatus includes an array of SRAM test cells. The test cells are configured according to a layout with NMOS and PMOS transistors coupleable as inverters and responsive to a first passing gate transistor. At least one of the NMOS and PMOS transistors of a test cell at a predetermined location in the array is coupled to a fixed voltage to force a logic state of an associated inverter. A switching signal coupled to the associated inverter through a second passing gate transistor produces a detectable test current through one of the NMOS and PMOS transistors of the associated inverter of said test cell and through one of the NMOS and PMOS transistors of an associated inverter of an adjacent series-connected test cell.

Claims20

Dependent claims

A static random access memory (SRAM) test apparatus comprising:

an array of SRAM test cells configured according to a layout with NMOS and PMOS transistors coupled as inverters and responsive to a first passing gate transistor, wherein at least one of the NMOS and PMOS transistors of a test cell at a predetermined location in the array is coupled to a fixed voltage to force a logic state of an associated inverter;
wherein a switching signal coupled to the associated inverter through a second passing gate transistor produces a detectable test current through one of the NMOS and PMOS transistors of the associated inverter of said test cell and through one of the NMOS and PMOS transistors of an associated inverter of an adjacent test cell connected in series with the test cell.

A method for configuring a test apparatus, comprising:

generating a first signal at a test signal generator;
coupling a track node to a positive power supply voltage via a first switch;
conducting the first signal to the first switch;
opening the first switch, based on the first signal, to decouple the track node from the positive power supply voltage;
providing a plurality of static random access memory (SRAM) test cells arranged in at least two rows and at least one column, each test cell including a first transistor (PG), a second transistor (PU), and a third transistor (PD), wherein a gate of one of the PU and PD transistors of each test cell is coupled to a fixed voltage to force said one transistor into a conducting state, and at least two of the test cells are connected in series,
closing the PG transistors of the series-connected test cells, based on the first signal, to couple the track node to a ground node via an electrical path through the series-connected test cells;
coupling the track node to the signal generator, to provide a second signal to the pulse generator;
and
detecting a current in said one transistor based on the second signal.

6 more elements

A method comprising:

generating a first signal at a test signal generator;
coupling a track node to a positive power supply voltage via a first switch;
conducting the first signal to the first switch;
opening the first switch, based on the first signal, to decouple the track node from the positive power supply voltage;
providing a plurality of static random access memory (SRAM) test cells coupled in parallel with one another, each test cell coupled to the track node, each test cell including a first transistor (PG), a second transistor (PU), and a third transistor (PD), wherein a gate of one of the PU and PD transistors of each test cell is coupled to a fixed voltage to force said one transistor into a conducting state;
closing the PG transistors of the test cells, based on the first signal, to conduct current from the track node through a predetermined one of the PU and PD transistors in each of the test cells;
and
coupling the track node to the signal generator, to provide a second signal to the pulse generator.

5 more elements

Dependencies are inferred from the claim text.

SRAM timing tracking circuit

Life of this patent

SRAM timing tracking circuit

Life of this patent

Abstract

Claims20