Differential ROM
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJack Liu
Life of this patent
Estimating the term…
Abstract
A differential read only memory array includes a differential sense amplifier coupled to first and second bit lines. A first bit cell is coupled to a first word line and to the first and second bit lines. The at least one bit cell includes a first transistor having a gate coupled to the first word line, a drain coupled to the first bit line, and a source coupled to a first power supply line. A second transistor has a gate coupled to the first word line. A source and a drain of the second transistor are either both connected to the second bit line or both unconnected to the second bit line.
Claims18
A differential read only memory array, comprising:
- a differential sense amplifier coupled to first and second bit lines;
- and
- at least one bit cell coupled to a first word line and to the first and second bit lines, the at least one bit cell including:
- a first transistor having a gate coupled to the first word line, a drain coupled to the first bit line, and a source coupled to a first power supply line;
- and
- a second transistor having a gate coupled to the first word line,
- wherein a source and a drain of the second transistor are directly coupled together and to the second bit line such that the source and drain are not directly connected to a power supply line.
A semiconductor memory, comprising:
- a plurality of differential sense amplifiers each coupled to a respective pair of bit lines;
- and
- a plurality of differential read only bit cells arranged in a plurality of rows and a plurality of columns, each of the plurality of rows associated with a respective word line, and each of the plurality of columns associated with a respective pair of bit lines,
- wherein a first bit cell is disposed in a first row and includes:
- a first transistor having a gate coupled to a first word line, a source coupled to a first power supply, and a drain coupled to the first bit line, wherein the first bit cell is configured to output a logic zero to the first bit line,
- a second transistor has a gate coupled to the first word line, and a source and a drain of the second transistor are both directly connected to the second bit line such that the source and drain are not directly connected to a power supply line.
Dependencies are inferred from the claim text.