Low power content-addressable memory and method

An Integrated Circuit (IC) comprising a content addressable memory (CAM) element pair comparison circuit that includes:

• a pair of CAM elements for storing binary values;
• the pair of CAM elements being logically coupled with four comparison lines such that only one comparison line will have a comparison value, the one comparison line having a comparison value being dependent on which of four binary vales is stored in the pair of CAM elements;
• a set of four match lines configured to receive a match value on only one of the four match lines for a comparison operation;
• and
• each of the four comparison lines being logically paired with one of the four match lines to define four output lines such that a positive match result value is output via an output line only on a condition that its respective match line has received the match value and its respective comparison line has the comparison value.

A method comprising:

• storing binary value pair a pair of content addressable memory (CAM) elements;
• providing a comparison signal to comparator circuitry that uniquely represents the stored binary values;
• inputting a match signal to the comparator circuitry that uniquely represents a binary value pair to be compared with the stored binary value pair;
• and
• operating a transistor to output a positive match result signal only on a condition that the comparison signal provided to the comparator circuitry and match signal input to the comparator circuitry represent the same binary value pair whereby no transistor of the comparator circuitry is operated when the comparison signal provided to the comparator circuitry and match signal input to the comparator circuitry represent different binary value pairs.