US 8,570,698 B2 · ESD protection for FinFETs

Abstract

An embodiment is a semiconductor device comprising a receiver circuit comprising fin field effect transistors (FinFETs), a transceiver circuit comprising FinFETs, and a transmit bus electrically coupling the receiver circuit and the transceiver circuit, wherein the receiver circuit and the transceiver circuit each further comprises an electrostatic discharge protection circuit comprising planar transistors electrically coupled to the transmit bus. Other embodiments may further comprise a power clamp electrically coupling a first power bus and a first ground bus, a power clamp electrically coupling a second power bus and a second ground bus, or at least two diodes electrically cross-coupling the first ground bus and the second ground bus. Also, the planar transistors of the transceiver circuit and the receiver circuit may each comprise a planar PMOS transistor and a planar NMOS transistor.

Claims20

Dependent claims

A method comprising:

receiving a charge in a first circuit, the first circuit comprising first operational circuitry and first protection circuitry, the first operational circuitry comprising a first fin field effect transistor (FinFET), the first protection circuitry comprising a first planar transistor;
passing a first current through the first planar transistor, the first current resulting from the charge that was received in the first circuit;
passing the first current through a transmit bus, the transmit bus being electrically coupled to a second circuit, the second circuit comprising second operational circuitry and second protection circuitry, the second protection circuitry comprising a second planar transistor;
passing the first current through the second planar transistor;
and
discharging the first current through a contact electrically coupled to the second circuitry.

3 more elements

A method comprising:

dissipating a charge received in a first circuit through a second circuit, wherein:
the first circuit comprises:
a first VDD supply bus,
a first VSS supply bus,
a first operational circuit comprising a first inverter, an input or output of the first inverter electrically coupled to a transmit bus, the first inverter comprising a first n-type finFET and a first p-type finFET, and
a first protection circuit comprising a first planar p-type FET (pFET) electrically coupled between the first VDD supply bus and the transmit bus, and comprising a first planar n-type FET (nFET) electrically coupled between the first VSS supply bus and the transmit bus, wherein one of the first planar pFET and the first planar nFET passes a first current resulting from the charge to or from the transmit bus;
and
the second circuit comprises:
a second VDD supply bus,
a second VSS supply bus,
a second operational circuit comprising a second inverter, an input or output of the second inverter electrically coupled to the transmit bus, the second inverter comprising a second n-type finFET and a second p-type finFET, and
a second protection circuit comprising a second planar pFET electrically coupled between the second VDD supply bus and the transmit bus, and comprising a second planar nFET electrically coupled between the second VSS supply bus and the transmit bus, one of the second planar pFET and the second planar nFET passes a first current to or from the transmit bus.

9 more elements

Dependencies are inferred from the claim text.

ESD protection for FinFETs

Life of this patent

ESD protection for FinFETs

Life of this patent

Abstract

Claims20