Scan method for liquid crystal display
AssigneeAu Optronics Corporation
InventorsHuan-Hsin Li, Yao-Jen Hsieh, Chih-Sung Wang
Life of this patent
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Abstract
A scan method for use in a flat panel display comprising K groups of lines, comprising the following steps. First, K sequences S1 to SK are provided. A scan order is then determined according to the K sequences S1 to SK. Thereafter, the K groups of lines are synchronously scanned by the scan order. K is an integer not less than 2. Each group of lines comprises at least M lines.
Claims17
A scan method for a flat panel display comprising Y lines divided into K groups, comprising:
- providing K sequences S1 to SK;
- determining an interlaced scan order by interlacing the K sequences S1 to SK;
- and
- synchronously scanning the K groups of lines based on the interlaced scan order such that each group of lines is scanned K times per Y scan time slots and the each group of lines is scanned alternately, and any two lines in each group of lines are not scanned at the same time in one scan slot;
- wherein K is an integer not less than 2, wherein:
- Si(x)=(x+Ni)(mod M), i=1 to K, x=1 to M;
- Where Si(x) denotes the xth element in sequence Si.
A timing controller, for a liquid crystal display comprising a plurality of lines, wherein:
- the timing controller divides Y lines into K groups;
- the timing controller provides K sequences S1 to SK and interlaces the K sequences S1 to SK to determine an interlaced scan order;
- the timing controller synchronously scans the K groups of lines based on the interlaced scan order such that each group of lines is scanned K times per Y scan time slots and the each group of lines is scanned alternately and any two lines in each group of lines are not scanned at the same time in one scan slot;
- K is an integer not less than 2, wherein:
- Si(x)=(x+Ni)(mod M), i=1 to K, x=1 to M;
- where Si(x) denotes the xth element in sequence Si.
A pixel driving circuit for a flat panel display, synchronously scanning Y lines divided into K groups, comprising:
- K gate drivers, each driving a corresponding group of lines;
- a timing controller, coupled to the K gate drivers, for controlling a processing order and image data;
- and
- a frame memory, coupled to the timing controller, for storing the image data;
- wherein
- the timing controller provides K sequences S1 to SK and interlaces the K sequences S1 to SK to determine an interlaced scan order;
- the timing controller synchronously scans the K groups of lines based on the interlaced scan order via the K gate drivers such that each group of lines is scanned K times per Y scan time slots and the each group of lines is scanned alternately and any two lines in each group of lines are not scanned at the same time in one scan slot;
- and
- K is an integer not less than 2, wherein:
- Si(x)=(x+Ni)(mod M), i=1 to K, x=1 to M;
- and
- where Si(x) denotes the xth element in sequence Si.
Dependencies are inferred from the claim text.