Method and apparatus for direct digital synthesis of signals using Taylor series expansion

A method of generating a Taylor series expansion of a sinusoid signal, comprising:

• receiving a phase angle value of a sinusoid, the phase angle value including a binary form;
• receiving most significant bits and least significant bits of the binary form phase angle value as inputs at one or more memory elements;
• using the most significant bits and the least significant bits as memory address locations to retrieve (i) from a first memory element a value of a first component in a Taylor series expansion, (ii) from a second memory element a value that when combined with a value retrieved from a third memory element represents a second component in the Taylor series expansion, and (iii) from a fourth memory element a value of a third component in the Taylor series expansion;
• converting outputs of the one or more memory elements to serial bitstreams for transmission;
• converting the serial bitstreams into parallel bitstreams for processing;
• combining the parallel bitstreams to generate the first component, the second component and the third component of the Taylor series expansion;
• and
• converting the first component, the second component and the third component of the Taylor series expansion to an analog output signal.

A non-transitory computer readable medium having stored therein instructions executable by a computing device to cause the computing device to perform operations comprising:

• receiving a phase angle value of a sinusoid, the phase angle value including a binary form;
• using most significant bits and least significant bits of the binary form phase angle value as memory address locations to retrieve (i) from a first memory element a value of a first component in a Taylor series expansion, (ii) from a second memory element a value that when combined with a value retrieved from a third memory element represents a second component in the Taylor series expansion, and (iii) from a fourth memory element a value of a third component in the Taylor series expansion;
• converting outputs of the one or more memory elements to serial bitstreams for transmission;
• converting the serial bitstreams into parallel bitstreams for processing;
• combining the parallel bitstreams to generate the first component, the second component and the third component of the Taylor series expansion;
• and
• converting the first component, the second component and the third component of the Taylor series expansion to an analog output signal.