Control circuit for connector

A circuit for controlling a connector to transmit data according to Low Pin Count (LPC) protocol or Joint Test Action Group (JTAG) protocol, the connector comprising first to tenth pins, the sixth pin of the connector connected to a standby power, the tenth pin of the connector grounded, the circuit comprising:

• a switch unit comprising a first terminal connected to the standby power through a first resistor, and a second terminal grounded;
• a first electronic switch comprising first to third terminals, wherein the first terminal of the first electronic switch is connected to the first terminal of the switch unit, the second terminal of the first electronic switch is connected to the standby power through a second resistor, the third terminal of the first electronic switch is grounded, the first electronic switch is turned on in response to the first terminal of the first electronic switch receiving a high level signal, the first electronic switch is turned off in response to the first terminal of the first electronic switch receiving a low level signal;
• a second electronic switch comprising first to third terminals, wherein the first terminal of the second electronic switch is connected to the second terminal of the first electronic switch, the second terminal of the second electronic switch is connected to the standby power through a third resistor, the third terminal of the second electronic switch is grounded, the second electronic switch is turned on in response to the first terminal of the second electronic switch receiving a high level signal, the second electronic switch is turned off in response to the first terminal of the second electronic switch receiving a low level signal;
• a first switch chip comprising first to fourth groups of data pins, and first and second enable pins, wherein each group of data pins comprises four data pins, the first group of data pins are respectively connected to first to fourth data pins of a Platform Controller Hub (PCH), three of the second group of data pins are respectively connected to a control pin, a reset pin, and a clock pin of the PCH, the rest data pin of the second group of data pins is grounded, the third group of data pins are respectively connected to the first to fourth pins of the connector, three of the fourth group of data pins are respectively connected to the seventh to ninth pins of the connector, the fourth data pin of the fourth group of data pins is grounded, the first and second enable pins are connected to the second terminal of the first electronic switch;
• the first group of data pins are electronically connected to the third group of data pins, and the second group of data pins are electronically connected to the fourth group of data pins, in response to the first and second enable pins receiving low level signals, the connector transmits data according to Low Pin Count (LPC) protocol;
• the first group of data pins are disconnected from the third group of data pins, and the second group of data pins are disconnected from the fourth group of data pins, in response to the first and second enable pins receiving high level signals;
• and
• a second switch chip comprising first and second groups of data pins, and an enable pin, wherein each group of data pins of the second switch chip comprises four data pins, the first group of data pins of the second switch chip are respectively connected to first to fourth data pins of a complex programmable logic device (CPLD), three of the second group of data pins of the second switch chip are respectively connected to the first to third pins of the connector, the fourth data pin of the second group of data pins of the second switch chip is connected to the fifth pin of the connector, the enable pin of the switch chip is connected to the second terminal of the second electronic switch;
• the first group of data pins are respectively electronically connected to the second group of the data pins of the second switch chip in response to the enable pin of the second switch chip receiving a low level signal, the connector transmits data according to JTAG protocol;
• the first group of data pins are disconnected to the second group of the data pins of the second switch chip in response to the enable pin of the second switch chip receiving a high level signal.