PVT-free calibration circuit for TDC resolution in ADPLL

An all digital phase locked loop (ADPLL), comprising:

• a controllable time-to-digital converter (TDC) having a plurality of variable delay elements, wherein the controllable TDC is configured to determine a phase difference between a frequency reference signal and a local oscillator clock signal and to generate a variable phase therefrom;
• a phase detector configured to determine a phase error comprising a difference between the variable phase and a reference phase received from a reference phase accumulator;
• a digitally controlled oscillator (DCO) configured to vary the phase of the local oscillator clock signal based upon the phase error;
• and
• a calibration unit configured to determine an effect of variations in PVT (process, voltage, and temperature) conditions based upon the phase error, and to generate a TDC tuning word that adjusts a delay introduced by one or more of the plurality of variable delay elements to mitigate the effect of the variations in PVT conditions.

A method, comprising:

• providing power to an all digital phase locked loop (APDLL) comprising a controllable time-to-digital converter (TDC) comprising a plurality of variable delay element;
• operating the controllable TDC to determining a phase difference between a frequency reference signal and a local oscillator clock signal and to generate a variable phase therefrom;
• determining an effect of variations in PVT (process, voltage, and temperature) conditions based upon the variable phase;
• and
• generating a TDC tuning word that adjusts a resolution of the controllable TDC to mitigate an effect of the variations in PVT conditions.