Methods and systems for programmable implementation of on-chip termination calibration

A system comprising:

• a first input/output pad;
• a second input/output pad;
• input/output circuitry comprising:
• a first differential input buffer circuitry, wherein:
• a first input of the first differential input buffer circuitry is coupled to the first input/output pad, and
• a second input of the first differential input buffer circuitry is coupled to the second input/output pad;
• and
• second differential input buffer circuitry, wherein:
• a first input of the second differential input buffer circuitry is coupled to the first input/output pad, and
• a second input of the second differential input buffer circuitry is coupled a reference voltage level;
• and
• control circuitry configured to control a controllably variable impedance provided by a termination circuitry based at least in part on an output voltage level of the first differential input buffer circuitry and based at least in part on an output voltage level of the second differential input buffer circuitry.

A method for using a circuit, the method comprising:

• providing first differential input buffer circuitry output signal by comparing, with first differential input buffer circuitry, a first signal level associated with an input/output pad with a second signal level;
• controlling the impedance associated with the input/output pad based at least in part on a voltage level of the first differential input buffer circuitry output signal;
• and
• providing second differential input buffer circuitry configured to output a second differential input buffer circuitry output signal by comparing the first signal level associated with the input/output pad with a third signal level, wherein:
• the third signal level is different from the second signal level,
• the control circuitry is further configured to control the impedance provided by the termination circuitry based at least in part on the second differential input buffer circuitry output signal,
• the first differential input buffer circuitry comprises high speed transceiver logic (HSTL) circuitry, and
• the second differential input buffer circuitry comprises low voltage differential buffer (LVDS) circuitry.