US 8,570,061 B2Granted

(N-1)-out-of-N voter mux with enhanced drive

AssigneeHoneywell International Inc.

InventorKeith Golke

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Abstract

This disclosure describes voting circuits where an output is generated based on a plurality of inputs. A first plurality of logic paths connects the output to a high voltage. Each logic path of the first plurality of logic paths includes two transistors. A second plurality of logic paths connects the output to the low voltage. Each logic path of the second plurality of logic paths comprises two transistors. Based on N or N−1 of the inputs agreeing, the output is driven to either the low voltage or the high voltage via a subset of logic paths of the first and second plurality of logic paths.

Claims15

Dependent claims

A circuit comprising:

a plurality of inputs;
an output;
a high voltage source;
a low voltage source;
a first plurality of logic paths connecting the output to the high voltage, wherein each logic path of the first plurality of logic paths comprises two transistors, wherein in response to a majority but not all of the plurality of inputs having a same value, two or more logic paths of the first plurality of logic paths enable current flow between the high voltage source and the output;
a second plurality of logic paths connecting the output to the low voltage, wherein each logic path of the second plurality of logic paths comprises two transistors, wherein a first logic path of the second plurality of logic paths comprises a first re-channel MOSFET and a second n-channel MOSFET, and wherein a second logic path of the second plurality of logic paths comprises the second n-channel MOSFET and a third n-channel MOSFET, and wherein
a source of the first n-channel MOSFET is connected to the low voltage source and a source of the third n-channel is connected to the low voltage source;
a drain of the first n-channel MOSFET is connected to a source of the second n-channel MOSFET and a drain of the third n-channel MOSFET is connected to the source of the second n-channel MOSFET;
and,
a drain of the second n-channel MOSFET is connected to the output.

7 more elements

A 2-out-of-3 voting circuit comprising:

a first input;
a second input;
a third input;
a high voltage source;
a low voltage source;
a first p-channel metal-oxide silicon field-effect transistor (MOSFET), wherein a source of the first p-channel MOSFET is connected to the high voltage source and a gate of the first p-channel MOSFET is connected to the first input;
a second p-channel MOSFET, wherein a source of the second p-channel MOSFET is connected to the high voltage source and a gate of the second p-channel MOSFET is connected to the third input;
a third p-channel MOSFET, wherein a source of the third p-channel MOSFET is connected to the high voltage source and a gate of the third p-channel MOSFET is connected to the second input;
a fourth p-channel MOSFET, wherein a source of the fourth p-channel MOSFET is connected to the high voltage source and a gate of the fourth p-channel MOSFET is connected to the first input;
a fifth p-channel MOSFET, wherein a source of the fifth p-channel MOSFET is connected to the high voltage source and a gate of the fifth p-channel MOSFET is connected to the third input;
a sixth p-channel MOSFET, wherein a source of the sixth p-channel MOSFET is connected to the high voltage source and a gate of the sixth p-channel MOSFET is connected to the second input;
a first n-channel MOSFET, wherein a source of the first n-channel MOSFET is connected to the low voltage source and a gate of the first n-channel MOSFET is connected to the first input;
a second n-channel MOSFET, wherein a source of the second n-channel MOSFET is connected to the low voltage source and a gate of the second n-channel MOSFET is connected to the third input;
a third n-channel MOSFET, wherein a source of the third n-channel MOSFET is connected to the low voltage source and a gate of the third n-channel MOSFET is connected to the second input;
a fourth n-channel MOSFET, wherein a source of the fourth n-channel MOSFET is connected to the low voltage source and a gate of the fourth n-channel MOSFET is connected to the first input;
a fifth n-channel MOSFET, wherein a source of the fifth n-channel MOSFET is connected to the low voltage source and a gate of the fifth n-channel MOSFET is connected to the third input;
a sixth n-channel MOSFET, wherein a source of the sixth n-channel MOSFET is connected to the low voltage source and a gate of the sixth n-channel MOSFET is connected to the second input;
a seventh p-channel MOSFET, wherein a source of the seventh p-channel MOSFET is connected to a drain of the first p-channel MOSFET and a drain of the second p-channel MOSFET and a gate of the seventh p-channel MOSFET is connected to the second input;
an eighth p-channel MOSFET, wherein a source of the eighth p-channel MOSFET is connected to a drain of the third p-channel MOSFET and a drain of the fourth p-channel MOSFET, and a gate of the eighth p-channel MOSFET is connected to the third input;
a ninth p-channel MOSFET, wherein a source of the ninth p-channel MOSFET is connected to a drain of the fifth p-channel MOSFET and a drain of the sixth p-channel MOSFET, and a gate of the ninth p-channel MOSFET is connected to the first input;
a seventh n-channel MOSFET, wherein a source of the seventh n-channel MOSFET is connected to a drain of the first n-channel MOSFET and a drain of the second n-channel MOSFET, and a gate of the seventh n-channel MOSFET is connected to the second input;
an eighth n-channel MOSFET, wherein a source of the eighth n-channel MOSFET is connected to a drain of the third n-channel MOSFET and a drain of the fourth n-channel MOSFET, and a gate of the eighth n-channel MOSFET is connected to the third input;
a ninth n-channel MOSFET, wherein a source of the ninth n-channel MOSFET is connected to a drain of the fifth n-channel MOSFET and a drain of the sixth n-channel MOSFET, and a gate of the ninth n-channel MOSFET is connected to the first input;
an output, wherein the output is connected to a drain of the seventh n-channel MOSFET, a drain of the eighth n-channel MOSFET, a drain of the ninth n-channel MOSFET, a drain of the seventh p-channel MOSFET, a drain of the eighth p-channel MOSFET, and a drain of the ninth p-channel MOSFET.

21 more elements

A 3-out-of-4 voting circuit comprising:

a first input;
a second input;
a third input;
a fourth input;
a high voltage source;
a low voltage source;
a first p-channel metal-oxide silicon field-effect transistor (MOSFET), wherein a source of the first p-channel MOSFET is connected to the high voltage source and a gate of the first p-channel MOSFET is connected to the first input;
a second p-channel MOSFET, wherein a source of the second p-channel MOSFET is connected to the high voltage source and a gate of the second p-channel MOSFET is connected to the second input;
a third p-channel MOSFET, wherein a source of the third p-channel MOSFET is connected to a drain of the first p-channel MOSFET and a drain of the second p-channel MOSFET, and a gate of the third p-channel MOSFET is connected to the third input;
a fourth p-channel MOSFET, wherein a source of the fourth p-channel MOSFET is connected to a drain of the first p-channel MOSFET and a drain of the second p-channel MOSFET, and a gate of the fourth p-channel MOSFET is connected to the fourth input;
a first n-channel MOSFET, wherein a source of the first n-channel MOSFET is connected to the low voltage source and a gate of the first n-channel MOSFET is connected to the first input;
a second n-channel MOSFET, wherein a source of the second n-channel MOSFET is connected to the low voltage source and a gate of the second n-channel MOSFET is connected to the second input;
a third n-channel MOSFET, wherein a source of the third n-channel MOSFET is connected to a drain of the first n-channel MOSFET and a drain of the second n-channel MOSFET, and a gate of the third n-channel MOSFET is connected to the third input;
a fourth n-channel MOSFET, wherein a source of the fourth n-channel MOSFET is connected to a drain of the first n-channel MOSFET and a drain of the second n-channel MOSFET, and a gate of the fourth n-channel MOSFET is connected to the fourth input;
an output, wherein the output is connected to a drain of the third n-channel MOSFET, a drain of the fourth n-channel MOSFET, a drain of the third p-channel MOSFET, a drain of the fourth p-channel MOSFET.

12 more elements

Dependencies are inferred from the claim text.

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Abstract