Semiconductor package with single sided substrate design and manufacturing methods thereof

A semiconductor package, comprising:

• a substrate unit including:
• a first patterned conductive layer having an upper surface;
• a first dielectric layer disposed adjacent to the upper surface of the first patterned conductive layer, the first dielectric layer exposing a part of the first patterned conductive layer to form a plurality of first contact pads;
• a second patterned conductive layer below the first patterned conductive layer and having a lower surface;
• a second dielectric layer between the first patterned conductive layer and the second patterned conductive layer, wherein:
• the second dielectric layer defines a plurality of openings extending from the first patterned conductive layer to the second patterned conductive layer;
• and
• the second patterned conductive layer includes a plurality of second contact pads exposed by the second dielectric layer;
• and
• a plurality of conductive posts, each of the plurality of conductive posts extending from the first patterned conductive layer to a corresponding one of the plurality of second contact pads through a corresponding one of the plurality of openings in the second dielectric layer, the each of the plurality of conductive posts filling the corresponding one of the plurality of openings in the second dielectric layer;
• wherein at least one of the plurality of conductive posts defines a cavity;
• a die electrically connected to the plurality of first contact pads, wherein the die is flip chip bonded to the plurality of first contact pads, wherein the die is connected to the plurality of first contact pads by a plurality of fused conductive bumps, and wherein the cavity is filled by a part of at least one of the plurality of fused conductive bumps;
• and
• a package body covering the first patterned conductive layer and the die.

A method of manufacturing a substrate, comprising:

• providing a carrier having an upper surface and a lower surface, and with a first conductive sheet formed adjacent to the upper surface of the carrier;
• forming a first plurality of conductive blocks made of copper or copper alloy extending vertically from the first conductive sheet, each of the first plurality of conductive blocks having an upper surface;
• forming a first dielectric layer that defines a first plurality of openings, each of the first plurality of openings exposing a part of the upper surface of a corresponding one of the first plurality of conductive blocks;
• and
• forming a first plurality of conductive posts and a first patterned conductive layer, each of the first plurality of conductive posts extending from a corresponding one of the first plurality of conductive blocks to the first patterned conductive layer and filling a corresponding one of the first plurality of openings.

A method of manufacturing a semiconductor package, comprising:

• providing a substrate including:
• a conductive sheet;
• a plurality of conductive blocks made of copper or copper alloy extending vertically from the conductive sheet, each of the plurality of conductive blocks having an upper surface;
• a dielectric layer that defines a plurality of openings, each of the plurality of openings exposing a part of the upper surface of a corresponding one of the plurality of conductive blocks;
• a patterned conductive layer;
• and
• a plurality of conductive posts, each of the plurality of conductive posts extending from a corresponding one of the plurality of conductive blocks to the patterned conductive layer and filling a corresponding one of the plurality of openings;
• electrically connecting a die to the patterned conductive layer;
• forming a package body covering the dielectric layer and the die;
• and
• removing the conductive sheet to expose the plurality of conductive blocks.

A substrate, comprising:

• a first patterned conductive layer having an upper surface;
• a first dielectric layer disposed adjacent to the upper surface of the first patterned conductive layer, the first dielectric layer exposing a part of the first patterned conductive layer to form a plurality of first contact pads;
• a second patterned conductive layer below the first patterned conductive layer and having a lower surface;
• a second dielectric layer between the first patterned conductive layer and the second patterned conductive layer, wherein:
• the second dielectric layer defines a plurality of openings extending from the first patterned conductive layer to the second patterned conductive layer;
• and
• the second patterned conductive layer includes a plurality of second contact pads and at least one trace;
• a third dielectric layer disposed on the second dielectric layer, the third dielectric layer exposing at least one of the plurality of the second contact pads and covering the at least one trace;
• and
• a plurality of conductive posts, each of the plurality of conductive posts extending from the first patterned conductive layer to a corresponding one of the plurality of second contact pads through a corresponding one of the plurality of openings in the second dielectric layer, the each of the plurality of conductive posts filling the corresponding one of the plurality of openings in the second dielectric layer.