Metal gate CMOS with at least a single gate metal and dual gate dielectrics

A semiconductor structure comprising:

• a semiconductor substrate including at least one nFET device region and at least one pFET device region, said device regions are separated by an isolation region;
• a first gate dielectric stack having a net dielectric constant greater than silicon dioxide located on a surface of said substrate and within said at least one nFET device region, wherein the first gate dielectric stack comprises a hafnium (Hf)-based dielectric layer on the semiconductor substrate and a layer of an alkaline earth metal-containing compound directly on the hafnium (Hf)-based dielectric layer, wherein the alkaline earth metal-containing compound is selected from the group consisting of MgO, MgS, MgF2, MgCl2, MgBr2, MgI2, CaO, CaS, CaF2, CaCl2, CaBr2, CaI2, SrO, SrS, SrF2, SrCl2, SrBr2, SrI2, BaO, BaS, BaF2, BaCl2, BaBr2, BaI2, and combination thereof;
• a second gate dielectric stack having a net dielectric constant greater than silicon dioxide located on a surface of said substrate and within said at least one pFET device region, wherein said second gate dielectric stack includes an aluminum containing dielectric layer, and wherein said first gate dielectric stack contains no net negative charge and said second gate dielectric stack contains no net positive charge;
• a first metal layer located on said first gate dielectric stack and said second gate dielectric stack;
• and
• a workfunction defining metal layer located on said first metal layer in one of said device regions, wherein in said at least one nFET device an nFET gate stack is provided that has a band edge workfunction and wherein in said at least one pFET device region a pFET gate stack is provided that has a ¼ gap workfunction.