Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least one gate level feature extending into adjacent gate level feature layout channel

A method for creating a layout of an integrated circuit, comprising:

• operating a computer to define a gate electrode level region having a number of adjacently positioned gate level feature layout channels, each gate level feature layout channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherein each of the number of adjacently positioned gate level feature layout channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a first line end spacing and a second end located adjacent to a second line end spacing, each gate level feature forming an electrically conductive path extending between its first and second ends, and wherein at least one gate level feature layout channel includes a gate level feature that extends into a neighboring gate level feature layout channel without contacting any other gate level feature within the neighboring gate level feature layout channel,
• wherein the gate electrode level region includes a first gate level feature that forms a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type,
• wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of only one transistor that is a second transistor of the first transistor type,
• wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of only one transistor that is a second transistor of the second transistor type, wherein the gate electrode of the second transistor of the second transistor type is substantially co-aligned with the gate electrode of the second transistor of the first transistor type along a first common line of extent in the first direction, and wherein the third gate level feature is separated from the second gate level feature by a first line end spacing as measured in the first direction,
• wherein the gate electrode level region includes a fourth gate level feature that forms a gate electrode of only one transistor that is a third transistor of the first transistor type,
• wherein the gate electrode level region includes a fifth gate level feature that forms a gate electrode of only one transistor that is a third transistor of the second transistor type, wherein the gate electrode of the third transistor of the second transistor type is substantially co-aligned with the gate electrode of the third transistor of the first transistor type along a second common line of extent in the first direction, and wherein the fifth gate level feature is separated from the fourth gate level feature by a second line end spacing as measured in the first direction,
• wherein the gate electrode level region includes a sixth gate level feature that forms a gate electrode of a fourth transistor of the first transistor type and a gate electrode of a fourth transistor of the second transistor type,
• wherein the second gate level feature is electrically connected to the fifth gate level feature, and wherein the third gate level feature is electrically connected to the fourth gate level feature,
• wherein the second and third transistors of the first transistor type are positioned between the first and fourth transistors of the first transistor type in the second direction,
• wherein the second and third transistors of the second transistor type are positioned between the first and fourth transistors of the second transistor type in the second direction,
• wherein the first, second, third, and fourth transistors of the first transistor type are collectively separated from the first, second, third, and fourth transistors of the second transistor type by an inner portion of the gate electrode level region, and
• wherein each of the second and third transistors of the first transistor type and each of the second and third transistors of the second transistor type has a respective diffusion region electrically connected to a common node.

A data storage device having program instructions stored thereon for generating a layout of an integrated circuit, comprising:

• program instructions for defining a gate electrode level region having a number of adjacently positioned gate level feature layout channels, each gate level feature layout channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherein each of the number of adjacently positioned gate level feature layout channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a first line end spacing and a second end located adjacent to a second line end spacing, each gate level feature forming an electrically conductive path extending between its first and second ends, and wherein at least one gate level feature layout channel includes a gate level feature that extends into a neighboring gate level feature layout channel without contacting any other gate level feature within the neighboring gate level feature layout channel,
• wherein the gate electrode level region includes a first gate level feature that forms a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type,
• wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of only one transistor that is a second transistor of the first transistor type,
• wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of only one transistor that is a second transistor of the second transistor type, wherein the gate electrode of the second transistor of the second transistor type is substantially co-aligned with the gate electrode of the second transistor of the first transistor type along a first common line of extent in the first direction, and wherein the third gate level feature is separated from the second gate level feature by a first line end spacing as measured in the first direction,
• wherein the gate electrode level region includes a fourth gate level feature that forms a gate electrode of only one transistor that is a third transistor of the first transistor type,
• wherein the gate electrode level region includes a fifth gate level feature that forms a gate electrode of only one transistor that is a third transistor of the second transistor type, wherein the gate electrode of the third transistor of the second transistor type is substantially co-aligned with the gate electrode of the third transistor of the first transistor type along a second common line of extent in the first direction, and wherein the fifth gate level feature is separated from the fourth gate level feature by a second line end spacing as measured in the first direction,
• wherein the gate electrode level region includes a sixth gate level feature that forms a gate electrode of a fourth transistor of the first transistor type and a gate electrode of a fourth transistor of the second transistor type,
• wherein the second gate level feature is electrically connected to the fifth gate level feature, and wherein the third gate level feature is electrically connected to the fourth gate level feature,
• wherein the second and third transistors of the first transistor type are positioned between the first and fourth transistors of the first transistor type in the second direction,
• wherein the second and third transistors of the second transistor type are positioned between the first and fourth transistors of the second transistor type in the second direction,
• wherein the first, second, third, and fourth transistors of the first transistor type are collectively separated from the first, second, third, and fourth transistors of the second transistor type by an inner portion of the gate electrode level region, and
• wherein each of the second and third transistors of the first transistor type and each of the second and third transistors of the second transistor type has a respective diffusion region electrically connected to a common node.