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US 8,569,837 B2Granted
MOS devices having elevated source/drain regions
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChih-Hsin Ko, Hung-Wei Chen, Chung-Hu Ke, Ta-Ming Kuan, Wen-Chin Lee
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Abstract
A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a deep source/drain region adjacent the gate electrode; a silicide region over the deep source/drain region; and an elevated metallized source/drain region between the silicide region and the gate electrode. The elevated metallized source/drain region adjoins the silicide region.
Claims18
A semiconductor structure comprising:
- a semiconductor substrate;
- a gate dielectric over the semiconductor substrate;
- a gate electrode over the gate dielectric;
- a deep source/drain region adjacent the gate electrode;
- a silicide region directly on a surface of the deep source/drain region;
- an elevated metallized source/drain region between the silicide region and the gate electrode, wherein the elevated metallized source/drain region adjoins the silicide region, wherein the silicide region has a different composition than the elevated metallized source/drain region;
- and
- a lightly doped source/drain (LDD) region underlying the elevated metallized source/drain region.
5 more elements
A semiconductor structure comprising:
- a semiconductor substrate;
- a gate dielectric over the semiconductor substrate;
- a gate electrode over the gate dielectric;
- a stressor in the semiconductor substrate and adjacent the gate electrode, an upper surface of the stressor being silicided;
- an elevated metallized source/drain region between the upper surface of the stressor and the gate electrode, wherein the elevated metallized source/drain region has a bottom surface substantially higher than a top surface of the semiconductor substrate, the elevated metallized source/drain region and the upper surface of the stressor comprising different materials;
- and
- a lightly doped source/drain (LDD) region underlying the elevated metallized source/drain region.
4 more elements
A semiconductor structure comprising:
- a semiconductor substrate comprising an NMOS region and a PMOS region;
- an NMOS device in the NMOS region, the NMOS device comprising:
- a first gate stack on the semiconductor substrate;
- a first spacer on a sidewall of the first gate stack;
- a first deep source/drain region adjacent the first gate stack;
- a first silicide region directly on a surface of the first deep source/drain region;
- a first elevated metallized source/drain region between the first silicide region and the first gate stack;
- and
- a first lightly doped source/drain (LDD) region underlying the first elevated metallized source/drain region;
- and
- a PMOS device in the PMOS region, the PMOS device comprising:
- a second gate stack on the semiconductor substrate;
- a second spacer on a sidewall of the second gate stack;
- a second deep source/drain region adjacent the second gate stack;
- a second silicide region directly on a surface of the second deep source/drain region;
- a second elevated metallized source/drain region between the second silicide region and the second gate stack, the second elevated metallized source/drain region comprising at least one different element than the second silicide;
- and
- a second lightly doped source/drain (LDD) region underlying the second elevated metallized source/drain region.
15 more elements
Dependencies are inferred from the claim text.