Accumulation field effect microelectronic device and process for the formation thereof

A gated microelectronic device comprising:

• a source
• with a source ohmic contact;
• said source
• having
• a source dopant type and
• a source dopant concentration and defining
• a source linear extent and
• a source thickness;
• a drain
• with a drain ohmic contact;
• said drain
• having a
• drain dopant type and
• drain dopant concentration and defining
• a drain linear extent and
• a drain thickness;
• a channel portion intermediate between said source and said drain,
• said channel portion
• having a
• channel portion dopant type and
• channel portion dopant concentration and defining
• a channel portion linear extent and
• a channel portion thickness,
• said channel portion being a thin film
• an insulative dielectric in contact with said channel portion;
• a gate in overlying contact with said insulative dielectric, said gate defining a gate-insulative dielectric interface;
• said channel portion having a dimension normal to the gate-insulative dielectric interface suitable to fully deplete in an off-state;
• a gate contact applying a gate voltage bias to control charge carrier accumulation and depletion in said channel portion;
• and
• the source dopant, the drain dopant, and the channel portion dopant being all of a same type;
• and
• wherein the source dopant concentration the channel dopant concentration, and the drain concentration are equivalent;
• wherein the source linear extent, the drain linear extent, and the positioning of the source ohmic contact and drain ohmic contact prevent ambipolar behavior in the device.

A gated microelectronic device comprising:

• an insulator substrate;
• a source
• supported on said insulator substrate, said source with a source ohmic contact;
• said source
• having
• a source dopant type and
• a source dopant concentration and defining
• a source linear extent and
• a source thickness;
• a drain
• supported on said insulator substrate, said drain with a drain ohmic contact;
• said drain
• having a
• drain dopant type and
• drain dopant concentration and defining
• a drain linear extent and
• a drain thickness;
• a channel portion intermediate between said source and said drain,
• said channel portion
• supported on said insulator substrate and
• having a
• channel portion dopant type and
• channel portion dopant concentration and defining
• a channel portion linear extent and
• a channel portion thickness,
• said channel portion being a thin film,
• said channel region normal to the gate-insulative dielectric interface having a dimension of between 5 and 100 nanometers;
• an insulative dielectric in contact with said channel portion;
• a gate in overlying contact with said insulative dielectric, said gate defining a gate-insulative dielectric interface;
• said channel portion having a dimension normal to the gate-insulative dielectric interface suitable to fully deplete in an off-state;
• a gate contact applying a gate voltage bias to control charge carrier accumulation and depletion in said channel portion;
• and
• the source dopant, the drain dopant, and the channel portion dopant being all of a same type and
• wherein the source dopant concentration the channel dopant concentration, and the drain concentration are equivalent;
• wherein the source linear extent, the drain linear extent, and the positioning of the source ohmic contact and drain ohmic contact prevent ambipolar behavior in the device.