Semiconductor device having vertical MOS transistor and method for manufacturing the semiconductor device

A semiconductor device including a vertical MOS (metal-oxide semiconductor) transistor, the vertical MOS transistor comprising:

• a semiconductor pillar formed in an area subjected to a shallow trench isolation layer of a semiconductor substrate,
• a lower diffusion layer formed shallower than a depth of a shallow trench isolation, in the semiconductor substrate at a lower portion of the semiconductor pillar,
• an upper diffusion layer formed at an upper portion of the semiconductor pillar,
• a channel part formed in a region sandwiched by the upper and lower diffusion layers,
• a gate insulating film and a gate electrode included on a side surface of the channel part;
• a conductive sidewall formed on a side surface of an insulating film of said shallow trench isolation;
• and
• an electrode electrically coupled to said conductive sidewall supplying a voltage to prevent said conductive sidewall from a floating state,
• wherein said electrode contacts the conductive sidewall via a gate electrode of a dummy transistor, the gate electrode of the dummy transistor comprising the conductive sidewall.

A semiconductor device including a vertical MOS (metal-oxide semiconductor) transistor, the semiconductor device comprising:

• an isolation layer formed in a semiconductor substrate to define an active area;
• a semiconductor pillar formed on said active area;
• a gate electrode formed above a sidewall of said semiconductor pillar to wholly surround said semiconductor pillar;
• a conductive layer formed above a sidewall of said isolation layer;
• and
• an electrode formed to be electrically coupled to said conductive layer.