US 8,569,826 B2Granted

Nonvolatile semiconductor memory device and method for manufacturing same

AssigneeKabushiki Kaisha Toshiba

InventorsMasaru Kidoh, Yoshiaki Fukuzumi

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Abstract

According to one embodiment, a nonvolatile semiconductor memory device includes a stacked structure, a select gate electrode, a semiconductor pillar, a memory layer, and a select gate insulating film. The stacked structure includes a plurality of electrode films stacked in a first direction and an interelectrode insulating film provided between the electrode films. The select gate electrode is stacked with the stacked structure along the first direction and includes a plurality of select gate conductive films stacked in the first direction and an inter-select gate conductive film insulating film provided between the select gate conductive films. The semiconductor pillar pierces the stacked structure and the select gate electrode in the first direction. The memory layer is provided between the electrode films and the semiconductor pillar. The select gate insulating film is provided between the select gate conductive films and the semiconductor pillar.

Claims16

Dependent claims

A nonvolatile semiconductor memory device comprising:

a first stacked structure including a plurality of first electrode films stacked in a first direction and a first interelectrode insulating film provided between the plurality of first electrode films;
a first select gate electrode stacked with the first stacked structure along the first direction, the first select gate electrode including a plurality of first select gate conductive films stacked in the first direction and a first inter-select gate conductive film insulating film provided between the plurality of first select gate conductive films;
a first semiconductor pillar piercing the first stacked structure, the plurality of first select gate conductive films and the first inter-select gate conductive film insulating film in the first direction;
a first memory layer provided between the plurality of first electrode films and the first semiconductor pillar;
a first inner insulating film provided between the first memory layer and the first semiconductor pillar;
a first outer insulating film provided between the first memory layer and the plurality of first electrode films;
and
a first select gate insulating film provided between the plurality of first select gate conductive films and the first semiconductor pillar.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/883,757Filed 16 Sep 2010
Priority: JP 2010-14023221 Jun 2010
Published: US 2011/0309431 A122 Dec 2011
Granted: 29 Oct 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10D 30/69
Insulated-gate field-effect transistors [IGFET]: iGFETs having charge trapping gate insulators, e.g. MNOS transistors
H10B 43/20
EEPROM devices comprising charge-trapping gate insulators: characterised by three-dimensional [3D] arrangements, e.g. with cells on different…
H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/40
EEPROM devices comprising charge-trapping gate insulators: characterised by the peripheral circuit region

Family

US 2011/0309431 A1Pre-grant publication · published 22 Dec 2011
US 8,569,826 B2This patent

From the US filing history. Foreign family members aren’t listed.

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