Three-dimensional CMOS circuit on two offset substrates and method for making same

A method for three-dimensional co-integration of a CMOS circuit successively comprising:

• providing a first crystalline substrate with a first main crystallographic direction, the first crystalline substrate comprising first field-effect transistors, the first field-effect transistor presenting a first source-drain axis oriented in a first secondary crystallographic direction of the first substrate;
• providing a second crystalline substrate with a second main crystallographic direction;
• covering the first crystalline substrate with the second crystalline substrate, the first field-effect transistors being disposed between the first crystalline substrate and the second crystalline substrate, the first main crystallographic direction and the second main crystallographic direction being offset before covering;
• and
• forming a second field-effect transistor on the second crystalline substrate, the second field-effect transistor presenting a second source-drain axis oriented in a second secondary crystallographic direction of the second crystalline substrate,
• wherein an angle between the first source-drain axis and the second source-drain axis is in a ]0, 90[ range.